有机场效应晶体管最新实验研究进展

介绍了近两年新报道的有机半导体材料,列举了其场效应性能参数;综述了有机场效应晶体管(OFET)在器件结构上的改进,重点阐述了基于常见有机功能层材料富勒烯及其衍生物、并五苯、聚3-己基噻吩的OFET对栅介质层及有机功能层与电极的界面的改进,讨论了器件结构改进对OFET阈值电压、开关比、载流子迁移率的影响;介绍了衬底温度、退火处理对OF-ET性能的影响。最后,针对有机场效应晶体管研究现状,指出未来研究中应注重开发高迁移率、高薄膜稳定性的有机功能材料和高介电常数、高成膜质量的有机栅介质材料,继续优化器件结构,改进制备工艺以提高器件性能。     

Dispersion characteristics of planar multilayer dielectric structures

Shifts in frequency of the dispersion characteristics of orthogonally polarized modes propagating in planar dielectric structures containing a wave-guiding substrate and layers of low-loss dielectric film are calculated. The influence of the geometric and real-valued parameters of thin semiconductor films located on the surfaces of the substrate or between two substrates on the mode’s phase shifts is studied.     

Device physics of capacitive MEMS

Using interferometric modulator (IMOD) MEMS-based technology as a typical example, we give an overview of key device concepts of capacitive micro-electro-mechanical systems (MEMS). We discuss basic electromechanical physics of the device, both in the ideal case of no charging in the dielectric and the more realistic scenario with charging. The dielectric stack is a critical element of capacitive MEMS. A significant part of the paper is dedicated to the role of the dielectric and electronic transport effects during device operation. The similarities and differences between dielectrics in MEMS and gate oxides in semiconductor MOS and MIM structures are highlighted. Several experimental techniques to study charge transport in the MEMS dielectric stack are reviewed following a discussion on how the dynamics of these electronic effects can be modeled. Finally, we comment on the importance of surface and interfaces on MEMS performance and reliability as well as fundamental studies of their properties.     

Porous Organic Field‐Effect Transistors for Enhanced Chemical Sensing Performances

The thin‐film structures of chemical sensors based on conventional organic field‐effect transistors (OFETs) can limit the sensitivity of the devices toward chemical vapors, because charge carriers in OFETs are usually concentrated within a few molecular layers at the bottom of the organic semiconductor (OSC) film near the dielectric/semiconductor interface. Chemical vapor molecules have to diffuse through the OSC films before they can interact with charge carriers in the OFET conduction channel. It has been demonstrated that OFET ammonia sensors with porous OSC films can be fabricated by a simple vacuum freeze‐drying template method. The resulted devices can have ammonia sensitivity not only much higher than the pristine OFETs with thin‐film structure but also better than any previously reported OFET sensors, to the best of our knowledge. The porous OFETs show a relative sensitivity as high as 340% ppm^?1 upon exposure to 10 parts per billion (ppb) NH₃. In addition, the devices also exhibit decent selectivity and stability. This general and simple strategy can be applied to a wide range of OFET chemical sensors to improve the device sensitivity.     

Influences of nonuniformity in metal concentration in gate dielectric silicate on CMIS inverters'' propagation delay time

It is shown that propagation delay time in CMIS (complementary metal insulator semiconductor field effect transistor) inverters is strongly affected by dielectric constant nonuniformity in gate dielectrics caused by the phase separation in silicate films. Influences of such nonuniformity on load capacitance are studied by analytical calculations based on a physical model which takes polarization into account. It is newly found that load capacitances are affected by the phase separation in qualitatively different ways, depending on the average metal concentration of their dielectric films. An experimental result is compared with those calculations. Influences of such nonuniformity on current drivability are studied by 3-dimensional device simulations. It is also newly found that such nonuniformity affects load capacitance and current drivability in different ways, resulting in an increase in propagation delay time of CMIS inverters for all metal concentrations studied. An explanation of this phenomenon is given with physical considerations.     

Mechanistic Considerations of Bending‐Strain Effects within Organic Semiconductors on Polymer Dielectrics

The development of organic transistors for flexible electronics requires the understanding of device behavior upon the application of strain. Here, a comprehensive study of the effect of polymer‐dielectric and semiconductor chemical structure on the device performance under applied strain is reported. The systematic change of the polymer dielectric results in the modulation of the effects of strain on the mobility of organic field‐effect transistor devices. A general method is demonstrated to lower the effects of strain in devices by covalent substitution of the dielectric surface. Additionally, the introduction of a hexyl chain at the peripheries of the organic semiconductor structure results in an inversion of the effects of strain on device mobility. This novel behavior may be explained by the capacitative coupling of the surface energy variations during applied strain.     

Capacitance of semiconductor p-n junction space-charge layers: anoverview

The modeling of capacitance of p-n junction space-charge layers in semiconductor devices is discussed. First, previously developed models and methods are reviewed. Capacitance models developed recently by the authors that include mobile-carrier, nonquasi static, and multidimensional effects are then considered. These models yield more accurate device and circuit simulations for semiconductor integrated circuits. The emphasis is on diodes and bipolar transistors, but many concepts used apply as well to p-n junctions of metal-oxide-semiconductor field effect transistors. The review includes conventional homojunction devices (devices fabricated with a single semiconductor such as silicon) and the increasingly important heterojunction devices (devices fabricated with two or more semiconductors or a semiconductor having a spatially varying chemical composition such as gallium-aluminum-arsenide)     

Hf-O-N and HfO2 barrier layers for Hf-Ti-O gate dielectric thin films

Hf-O-N and HfO₂ thin films were evaluated as barrier layers for Hf-Ti-O metal oxide semiconductor capacitor structures. The films were processed by sequential pulsed laser deposition at 300 °C and ultra-violet ozone oxidation process at 500 °C. The as-deposited Hf-Ti-O films were polycrystalline in nature after oxidation at 500 °C and a fully crystallized (o)-HfTiO₄ phase was formed upon high temperature annealing at 900 °C. The Hf-Ti-O films deposited on Hf-O-N barrier layer exhibited a higher dielectric constant than the films deposited on the HfO₂ barrier layer. Leakage current densities lower than 5 × 10 A/cm² were achieved with both barrier layers at a sub 20 Å equivalent oxide thickness.     

Study of oriented growth of oligofluorene–thiophene films onto aligned vacuum-deposited polytetrafluoroethylene layers

An analysis of a vacuum-deposited fluorene-thiophene-based material 5,5′-Di(9,9′-di-(butyl)-fluorene-2,2′-bithiophene) (DBFBT) onto different substrates, which can act as dielectric gate for organic field-effect transistor is made. Also a new method for preparation of high-quality dielectric thin films made of polytetrafluoroethylene (PTFE) is described. This method includes film formation by means of a special kind of vacuum deposition polymerization (VDP) of PTFE, assisted by electron cloud activation. Rubbing of these layers makes them orienting substrate materials which induce spontaneous ordering of deposited organic semiconductor layers. We investigated structure and morphology of PTFE layers deposited by vacuum process in dependence on deposition parameters: deposition rate, deposition temperature, electron activation energy and activation current. The molecular structure of the PTFE films was investigated by use of infrared spectroscopy. By means of ellipsometry, values of refractive index between 1.33 and 1.36 have been obtained for PTFE films in dependence on deposition conditions. Using the cold friction technique orienting PTFE layers with unidirectional grooves are obtained. We have shown that DBFBT layers growth on top of rubbed PTFE films present a certain alignment suitable for building organic field-effect transistors with better transport parameters.     

Scaling of multidielectric nonvolatile SONOS memory structures

Present-day low-power, portable lap-top computers and consumer products require non-volatile semiconductor memory (NVSM) operating at 5 V with a trend towards reducing this level to 3.3 V. The SONOS technology, an acronym for the polySilicon-blocking Oxide-Nitride-tunnel Oxide-Silicon structure used in capacitors and transistors, shows promise as a technology for present and future low voltage NVSM applications. The nitride layer in the dielectric sandwich permits the storage of charge resulting in adjustable threshold voltages. This paper examines the physics and characterization of scaled SONOS NVSM transistors in relation to reducing the programming voltage. We develop a model for the transient characteristics of the SONOS NVSM transistor with: (1) a simple closed-form solution valid for short programming times; and (2) a numerical solution covering the entire range of programming times. The simple closed-form solution clearly illustrates the dependence of the turn-on time and erase/white slope on the dielectric thicknesses, initial stored charge in the nitride, and programming voltage. In particular, we have examined: (1) decreasing the tunnel oxide thickness; and (2) scaling the blocking oxide thickness. By properly scaling the dielectric films (11 Å tunnel oxide, 50 Å nitride, 40 Å blocking oxide), a ±8 V programmable SONOS device has been obtained with a 50 μs write time and a 100 μs erase time for a 3 V memory window, and a ±5 V programmable device with a 100 ms erase and write time for a 1.5 V memory window.     

Nanofabrication with proximal probes

In this paper, we describe the use of proximal probes, such as the atomic force microscope (AFM) and the scanning tunneling microscope (STM), for nanofabrication. A resistless proximal probe-based lithographic technique has been developed that uses the local electric field of an STM or conductive AFM tip that is operated in air to selectively oxidize regions of a sample surface. The resulting oxide, typically 1-10 nm thick, can be used either as a mask for selective etching or to directly modify device properties by patterning insulating oxides on thin conducting layers. In addition to this resistless approach, we also describe the use of the STM/AFM to modify the chemical functionality of self-assembling monolayer films. Such modified films are used as a template for the selective electroless plating of metal films. The above processes are fast simple to perform, and well suited for device fabrication. We apply the anodic oxidation process to the fabrication of both semiconductor and metal-oxide devices. In these latter structures, sub-10 nm-sized device features are easily achieved, and we describe the fabrication of the smallest possible device, a single, atomic-sized metallic point contact by using in situ-controlled AFM oxidation     

Influence of dielectric constant distribution in gate dielectrics on the degradation of electron mobility by remote Coulomb scattering in inversion layers

It has been reported that mobility in high-/spl kappa/ gate dielectric metal-insulator semiconductor field-effect transistors is lower than that in conventional metal-oxide semiconductor field-effect transistors and the reason for this degradation has been considered to be the fixed charge in dielectric films as well as remote phonon scattering. We investigated the influence of dielectric constant distribution in gate dielectrics on electron mobility determined by remote Coulomb scattering (/spl mu//sub RCS/) using numerical simulations and a physical model. It is shown that electron mobility in the inversion layer is strongly affected by the dielectric constant distribution in gate dielectrics. In the case of stacked-gate dielectrics of a high-/spl kappa/ film and an interfacial layer, mobility has a minimum as the dielectric constant of the interfacial layer increases while it increases virtually monotonically with dielectric constant of the high-/spl kappa/ film. These phenomena are explained, considering the electrical potential in the substrate induced by fixed charges in gate dielectrics using the Born approximation. Preferable dielectric constant distribution is presented in terms of the suppression of the remote Coulomb scattering.     

Steady-state characteristics of two terminal inversion-controlled switches

The important fabrication procedures and the direct current-voltage characteristics of metal/conducting “insulator”/semiconductor junction diodes are described. These devices generally have two impedance states. The high impedance state is associated with a steady-state deep depletion of the semi-conductor surface which permits the device to absorb a high voltage. The low-impedance state is associated with a partial inversion of the semiconductor surface which greatly increases the electric field across the insulator, even though only a low voltage exists across the device. The generality of this phenomenon is emphasized by citing results from a wide variety of combinations of insulator materials and semiconductor structures. Uniformity of conductor through the insulator and ruggedness of the device are discussed in detail. The device's I–V characteristics can either be independent or quite sensitive to ambient temperature. The temperature sensitivity is explained by the effects of temperature on those mechanisms which control the formation of inversion layers.     

The all-metal spin transistor

An entirely new kind of switching device is fabricated entirely from metals. The three-layer, three-terminal spin transistor behaves somewhat like a semiconductor bipolar transistor; though the physical operating principles differ. The emitter and collector layers of the spin transistor are ferromagnetic films. The base layer is a nonmagnetic metal, such as gold, copper, or silver. Being all-metal the device can be made much smaller than semiconductor transistors-less than 0.1 micrometer on a side. Although still a technological infant, the device has the electrical properties required by memory cells, current amplifiers, and logic circuits. A computer made only of metals seems quite possible     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

A Review on Dielectric Breakdown in Thin Dielectrics: Silicon Dioxide,High‐k,and Layered Dielectrics

Thin dielectric films are essential components of most micro‐ and nanoelectronic devices, and they have played a key role in the huge development that the semiconductor industry has experienced during the last 50 years. Guaranteeing the reliability of thin dielectric films has become more challenging, in light of strong demand from the market for improved performance in electronic devices. The degradation and breakdown of thin dielectrics under normal device operation has an enormous technological importance and thus it is widely investigated in traditional dielectrics (e.g., SiO₂, HfO₂, and Al₂O₃), and it should be further investigated in novel dielectric materials that might be used in future devices (e.g., layered dielectrics). Understanding not only the physical phenomena behind dielectric breakdown but also its statistics is crucial to ensure the reliability of modern and future electronic devices, and it can also be cleverly used for other applications, such as the fabrication of new‐concept resistive switching devices (e.g., nonvolatile memories and electronic synapses). Here, the fundamentals of the dielectric breakdown phenomenon in traditional and future thin dielectrics are revised. The physical phenomena that trigger the onset, structural damage, breakdown statistics, device reliability, technological implications, and perspectives are described.     

Reliability issues of double gate dielectric stacks based on hafnium dioxide (HfO2) layers for non-volatile semiconductor memory (NVSM) applications

In this study, we present selected reliability issues of double gate dielectric stacks for non-volatile semiconductor memory (NVSM) applications. Fabricated gate structures were consisted of PECVD silicon oxynitride layer (SiO_xN_y) as the pedestal layer and hafnium dioxide layer (HfO₂) as the top gate dielectric. In the course of this work, obtained MIS structures were investigated by means of current–voltage characteristics, as well as applying dc stresses in constant current (CCS) and voltage (CVS) mode. Presented results have shown that the application of ultra-thin PECVD silicon oxynitride layer results in significant increase of breakdown voltage value in comparison to MIS structure with only hafnia as the gate dielectric. Moreover, due to the high temperature annealing of deposited SiO_xN_y layers, MIS device demonstrates much lower leakage currents, as well as higher breakdown voltage values in comparison to device with ‘as-deposited’ SiO_xN_y bottom layer. The results also proved larger immunity to dc stresses and better retention characteristics of MIS devices with ‘annealed’ oxynitride, in comparison to ‘as-deposited’ pedestal layer.     

Interfacial Characterization and Transport Conduction Mechanisms in Al|HfO2|p-Ge Structures: Energy Band Diagram

Semiconductors - Ge-based metal-oxide semiconductor structures exhibiting thin ALD-grown high-k dielectric HfO2 films were fabricated and characterized chemically, structurally, and electrically....