Temperature dependence of latch-up phenomena in scaled CMOS structures

In this paper the temperature dependence of latch-up in a VLSI CMOS technology is studied. Both steady-state and pulse-induced dynamic trigger characteristics are presented showing a marked increase in latch-up resistance with decreasing temperature; in particular, a latch-up free condition is met for several structures at temperatures ranging between 100 and 200 K. The results of measurements of parasitic bipolar parameters and shunting resistances at different temperatures are reported, and their values are related to latch-up characteristics.     

A structure-oriented model for determining the substrate spreading resistance in bulk CMOS latch-up paths and its application in holding current prediction

A structure-oriented model has been developed to simulate the actual distribution of majority-carrier current flow paths in the substrate when the parasitic p-n-p-n structure with long-stripe geometry in a CMOS (complementary metal—oxide-semiconductor) circuit is at the latch-up state. Based on this structure-oriented model, the voltage drop across the latch-up path in the substrate can be calculated directly from the structure data. Therefore, the equivalent emitter-base shunting resistance in the substrate can be easily obtained and used to accurately predict the holding current. The two-dimensional numerical simulations have been carried out, based on this structure-oriented model, to obtain the emitter-base shunting resistance associated with the parasitic lateral bipolar transistor in the substrate. The computed substrate shunting resistance and the well emitter-base shunting resistance have been used to calculate the holding current with the help of the measured peak parasitic transistor gains. The predicted holding currents have been found to be in good agreement with the experimental data measured from several p-n-p-n structures, including normal and reversed layouts which are all designed by using the long-stripe geometries. Furthermore, the numerical simulations have been extended to predict the effects of the layout changes of the p-n-p-n structures on the latch-up susceptibility.     

The modified structure of the lateral IGBT on the SOI wafer forimproving the dynamic latch-up characteristics

The modified structure of the lateral IGBT(LIGBT) on an SOI wafer for improving the dynamic latch-up characteristics is presented together with its numerical simulations and experimental results. The modified LIGBT structure has a p⁺-emitter layer between the collector and gate regions. The current at which the latch-up occurs during the turn-off transient under an inductive load is estimated in comparison with that of the conventional LIGBT. The dynamic latch-up current at room temperature and 125°C for the modified LIGBT were 350 A/cm² and 290 A/cm², respectively. These results indicate the improvement of about 3.5 times at room temperature and about 5.5 times at 125°C compared with those for the conventional LIGBT. This remarkable improvement in the dynamic latch-up performance is accomplished at the expense of an increase of 0.8 V in the forward voltage drop     

Latch-up and image crosstalk suppression by internal gettering

Internal gettering can be used to reduce crosstalk in imagers and latch-up susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for the crosstalk reduction obtained in an area imager. Also, the current gain β of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1/β, in accordance with the theory. A Monte Carlo method was developed to calculate the expected lateral transistor current gain. The calculated β's are in excellent agreement with the measured values.     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。文章首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图设计和工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应的关键技术方案。     

The transient analysis of latch-up in CMOS transmission gate induced by laser

An analytical model of transient latch-up in CMOS transmission gate induced by laser is established. The time-dependent current characteristics of the parasitic silicon controlled rectifier (SCR) under different injected photocurrent are illustrated. The model analyzes the trigger conditions for latch-up and describes the dynamic process varying with time. The photocurrent threshold causing latch-up under different pulse widths and repetition frequencies is obtained, which agrees well with the experimental results reported in the literature.     

An efficient method for calculating the d.c. triggering currents in CMOS latch-up

The substrate and well resistances have been calculated from the structure parameters of the fabricated CMOS structures. Based on the ideal diode model and the calculated resistances, the d.c. triggering currents for CMOS latch-up due to the voltage undershoot and overshoot on the parasitic emitters have been calculated. The calculated d.c. triggering currents have been compared with experimental measurements and good agreement has been obtained. Therefore, the proposed method is efficient in calculating the d.c. triggering currents.     

A switched-current, switched-capacitor temperature sensor in0.6-μm CMOS

A temperature-to-digital converter is described which uses a sensor based on the principle of accurately scaled currents in the parasitic substrate p-n-p in a standard fine-line CMOS process. The resulting PTAT δV_BE signal is amplified in an auto-zeroed switched-capacitor circuit, sampled, and converted to a digital output by a low-power 10-bit SAR ADC providing a resolution of 0.25° from -55°C to 125°C with an error of less than 1°. A single adjustment of temperature error is provided for wafer probe. No further calibration is required. A switching bandgap reference circuit will also be described which uses similar techniques to generate an accurate low-noise reference voltage for the ADC. The circuits are part of a multichannel data-acquisition system where other input voltages must also be sampled and measured, and so the speed and power of the ADC is not determined by the temperature sensor alone. For continuous operation, the supply current is 1 mA, but a low-power mode is provided where the part is normally in shut down and only powers up when required. In this mode, the average power supply current at 10 conversions/s is 0.3 μA. The supply voltage is 2.7-5.5 V     

Application of transient interferometric mapping method for ESD and latch-up analysis

Transient Interferometric Mapping (TIM) tools are reviewed from a perspective of their particular application area and comparison to other transient optical analysis techniques. TIM studies on trigger behavior, current filamentation and failure modes in BCD DMOS and ESD protection devices under TLP and system-level-ESD – like pulses are overviewed. TIM analysis of CMOS ESD protection devices, in particular study of on-state spreading effect in 90 nm SCRs is also presented. Furthermore TIM investigations of substrate currents and parasitic SCR paths during transient latch-up events in 90 nm CMOS and BCD technology test structures and products are reviewed. Finally TIM studies of ESD and short-time self-heating phenomena in GaN HEMTs and lasers are also briefly mentioned.     

The effect of 1300-1380°C anneal temperatures and materialcontamination on the characteristics of CMOS/SIMOX devices

The characteristics of CMOS transistors fabrication on silicon implanted with oxygen (SIMOX) materials were measured as a function of the silicon superficial layer contamination levels. In addition, postimplant anneal temperatures of 1300°C, 1350°C, and 1380°C were examined. It is found that the transistor leakage currents as well as the integrity of the gate oxide and implanted SIMOX oxide are functions of the carbon content in the starting material. Leakage currents below 1.0×10^-12 A/μm of channel width have been measured when the carbon concentration is reduced to 2×10¹⁸/cm². In addition, the integrity of the transistor gate dielectric, SIMOX implanted oxide, and oxygen precipitate density are seen to be a function of the postimplant anneal temperature. A gate dielectric breakdown field of 10 MV/cm has been achieved when the postimplant temperature is increased to 1380°C     

High-coupling-efficient 1.3-μm laser diodes with goodtemperature characteristics

We have proposed uniformly beam-expanded structures based on the advanced concept for realizing high coupling efficiency and good temperature characteristics. Beam expansion (optical confinement reduction) by narrowing the core layer width as well as a carrier confinement are strongly enhanced by adopting a larger bandgap InGaAsP for MQW barriers and separate confinement heterostructure layers. These laser diodes (LD's) were fabricated by the conventional buried heterostructure laser process, which is very important in reducing the cost. Our results have proven the effectiveness of our proposition. The LD's with high coupling efficiency (-3.2 dB) and good temperature characteristics have been achieved even using the simple approach of reducing optical confinement. The threshold currents at 25 and 85°C are 9.3 and 39.4 mA, respectively. The slope efficiency at 25°C is 0.39 W/A and still high (0.26 W/A) even at 85°C     

CMOS电路结构中的闩锁效应及其防止措施研究

CMOS Scaling理论下器件特征尺寸越来越小,这使得CMOS电路结构中的闩锁效应日益突出。闩锁是CMOS电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致器件失效。首先分析了CMOS电路结构中效应的产生机理及其触发方式,得到了避免闩锁效应的条件。然后通过对这些条件进行分析,从版图、工艺等方面考虑如何抑制闩锁效应。最后介绍了几种抑制闩锁效应关键技术方案。     

一种Bipolar结构中的闩锁效应

闩锁是集成电路结构所固有的寄生效应,这种寄生的双极晶体管一旦被外界条件触发,会在电源与地之间形成大电流通路,导致整个器件失效。文章较为详细地阐述了一种Bipolar结构中常见的闩锁效应,并和常见CMOS结构中的闩锁效应做了对比。分析了该闩锁效应的产生机理,提取了用于分析闩锁效应的等效模型,给出了产生闩锁效应的必要条件与闩锁的触发方式。通过对这些条件的分析表明,只要让Bipolar结构工作在安全区,此类闩锁效应是可以避免的。这可以通过版图设计和工艺技术来实现。文章最后给出了防止闩锁效应的关键设计技术。     

Latch-up and image crosstalk suppression by internal gettering [in CMOS]

Internal gettering can be used to reduce crosstalk in imagers and latchup susceptibility in CMOS circuits. The internal gettering process forms defects in the bulk of the silicon wafers that are effective recombination sites for minority carriers in the substrate. Experimental and theoretical results are presented for crosstalk reduction obtained in an area imager. The current gain /spl beta/ of the parasitic lateral n-p-n transistors formed in the substrate in CMOS circuits was considerably lower for the internally gettered wafers. The trigger current needed to initiate latch-up in the n-p-n-p structures increased as 1//spl beta/, in accordance with the theory. A Monte Carlo method was developed to calculate the expected transistor current gain. The calculated /spl beta/s are in excellent agreement with the measured values.     

Efficient room-temperature continuous-wave AlGaInP/AlGaAs visible(670 nm) vertical-cavity surface-emitting laser diodes

Significant improvement in the performance of AlGaInP/AlGaAs visible vertical-cavity surface-emitting laser diodes has been achieved in gain-guided planar-geometry devices utilizing proton implants to define the current injection path. Threshold currents as low as 1.25 mA were measured on 10 μm-diameter devices, with maximum power output of 0.33 mW from larger devices. Continuous-wave (cw) lasing was achieved at temperatures as high as 45°C. The improved diode performance is attributed to better lateral heat-sinking and reduced parasitic heat generation afforded by the planar device structure, relative to previously-reported air-post structures. This work represents the first realization of efficient room-temperature operation of AlGaInP-based visible VCSEL diodes     

Thermal implications of high SARs in the body extremities at theANSI-recommended MF-VHF safety levels

Surface-temperature elevation of the wrist and the ankle sections were measured for a healthy human subject at room temperature (22-25°C) for a variety of RF currents and SARs (specific absorption rate) in the frequency band 1-50 MHz. The observed highest rates of temperature increase in °C/min are given by the best-fit relationships: 0.0045×SAR in W/kg for the ankle section and 0.0048×SAR for the wrist section, the latter being involved for conditions of contact with ungrounded bodies like cars, trucks, fences, etc. Since ankle-section SARs on the order of 182-243 W/kg and wrist-section SARs as high as 1045 W/kg have previously been projected for the E fields recommended in the ANSI C95.1-1982 safety guide, fairly high rates of temperature increase are anticipated     

High temperature performance and operation of HFETs

The high temperature performance of Al_0.75Ga_0.25 As/In_0.25Ga_0.75As/GaAs Complementary Heterojunction FETs (CHFETs) is reported between 25 and 500°C. Both experimental and modeled devices have shown acceptable digital characteristics to 400°C. Digital logic circuits have also been shown to operate at temperatures of over 400°C. This strongly suggests that GaAs based devices are capable of satisfying high temperature electronics requirements in the 125-400°C range. Two dimensional physically based modeling has been used to understand the high temperature operation of the HFETs. This work has shown that the devices suffer from gate limited drain leakage currents at elevated ambient temperatures. This off-state leakage current is higher than anticipated. Simulation has shown that, although forward gate leakage currents are reduced with the heterostructure device design, the reverse current is not     

Numerical analysis of heavy ion particle-induced CMOS latch-up

Heavy ion particle-induced CMOS latch-up is analyzed using a two-dimensional transient numerical simulator. The charge funneling effect during the carrier collection process is found to lower the parasitic bipolar emitter-base potential barrier. This parasitic bipolar action is the main factor initiating latch-up. Latch-up susceptibility is then examined as a parameter of the heavy ion particle incident condition.     

A practical high-latchup immunity design methodology for internalcircuits in the standard cell-based CMOS/BiCMOS LSIs

A practical high-latchup-immunity design methodology is proposed for high-density internal circuits in standard cell-based CMOS/BiCMOS LSIs. Both locally injected trigger current and uniformly generated trigger current were measured using a new test structure. Focusing on the difference in the well shunt resistance between local and uniform trigger currents, a practical latchup-free guideline based on an analytical model for uniformly generated trigger current in the well is presented for the periodic placement of well contacts dependent on parasitic device parameters, on generated trigger current level, and a layout pattern size     

An efficient numerical model of CMOS latch-up

A one-dimensional numerical model of latch-up in bulk CMOS structures is presented. The model simulates the triggering and sustaining regimes of the parasitic SCR, yielding results nearly equivalent to those obtained using two-dimensional analysis, but with two orders of magnitude-lower computational cost. The model is used to obtain the SCR switching characteristics of typical CMOS based on two-dimensional impurity cross sections, and parameter sensitivities are examined.