Thermal dependence of HBT high-frequency performance

The effects of power dissipation and thermal resistance on device junction temperature are introduced for the first time in modelling the high-frequency performance of heterojunction bipolar transistors (HBTs). Simulated low-bias (V/sub cb/=0 V)f/sub T//J/sub c/ characteristics using the proposed model are consistent with previously reported results. This model extends previous calculations to include typical high-bias operating conditions where dramatic thermal effects are demonstrated.<>     

Anomalous BTI effects in n-type integrated power transistors

A novel bias-temperature-instability effect is observed in n-type integrated power transistors. The effect is enhanced by the total internal temperature of the device as well as by the oxide electric field. The total temperature that the device is experiencing is the sum of the ambient temperature and the temperature increase due to power dissipation. The latter is found to be the dominant effect in power transistors integrated in deep submicrometer technologies. A model is presented to calculate the safe operating area of the transistors.     

Thermal management for high-power photonic crystal light emitting diodes

An effective heat dissipation structure is a crucial element for stable thermal management in ensuring thermal stability of high power photonic crystal light emitting diodes (PC-LEDs). New integrated structure for effective thermal management is put forward for high power PC-LEDs to reduce the thermal resistance between the chip and heat dissipation device, which can be composed by the heat pipes or an active heat dissipation device. Based on the thermal resistances analyzed, 3D thermal distributions for the device CSM360 with the nominal electric power of 80 W are simulated and analyzed by using of ANSYS. Compared with the general metal fins model, the heat pipes integrated model improves the heat dissipation efficiency of CSM360 by 36.61%, while the active heat dissipation device integrated model improves the heat dissipation efficiency by 60.2% at the temperature of 50 °C on the cold end of the device. The results show that the integrated structure can obtain a significant improvement in thermal management and achieve a reduction in temperature in the working status of CSM360. Heat dissipation experiments are also conducted, and the values of temperature distributions are validated to be coincident with those from simulations.     

Time-dependent carrier flow in a transistor structure under nonisothermal conditions

A time-dependent temperature-dependent two-dimensional model has been developed to illustrate the internal behavior of bipolar transistors. Electrothermal interactions within the device are calculated in an attempt to better understand thermal instability modes. Numerically computed results are presented showing the electrical and thermal effects in the transistor operating in the switching mode during turn-on along a resistive load line. Plots of current density, electrostatic potential, and temperature versus time illustrate the combined effects of electrical rise time, thermal delay time, electrothermal interaction, current crowding, current spreading, conductivity modulation, and base pushout in bipolar transistors.     

基于结构函数的功率MOSFET器件热阻研究

热阻是衡量功率MOSFET器件散热能力的重要参数,对其准确测试与分析具有重要意义。基于结构函数理论,同一功率MOSFET器件在不同条件下进行两次实验,通过积分结构函数分离点来确定器件热阻。该方法简单准确,可重复性好,实验测试结果为0.5 K/W,与有限元(FE)建模获得的0.44 K/W符合较好。对比两不同批次器件的微分结构函数,其中一种器件微分结构函数发生0.2 K/W偏移,超声波扫描(SAM)发现该器件焊料层存有空洞,该方法可用来判断器件内部工艺的好坏。     

Thermal analysis of active layer in organic thin-film transistors

This paper reports on the direct thermal observation of the pentacene – based organic thin-film transistors (OTFTs) under the real operating conditions. Liquid crystal (LC) spreading method was utilized for the thermal investigation of an active layer of the OTFT package. Temperature variation in the OTFT package was recorded for the different input power and significant heat generation was observed in the confined active layer. Detailed thermal performance of the OTFT package was projected using a Computational Fluid Dynamics (CFD) method as well. It was shown that the driving of the OTFT package with the drain voltage of ?15 V resulted in the active layer temperature of about 53.2 °C. The result indicates that the device design with effective thermal dissipation is imperative for reliable operation of the OTFT package.     

A quantitative study of emitter ballasting

A theoretical and experimental study is carried out to quantitatively analyze the effect of emitter ballasting on thermal instabilities in high power density transistors. The analysis includes factors such as thermal resistance, emitter and base resistances, collector dissipation, etc., affecting thermal runaway. In particular, numerical computations are presented to describe current-voltage characteristics as they relate to thermal instability with emitter ballast resistance and the collector bias voltage as parameters. The agreement between theory and experiment is shown to be excellent. The study yields a minimum value of ballast resistance above which there is unconditional thermal stability.     

Two-dimensional carrier flow in a transistor structure under nonisothermal conditions

A two-dimensional mathematical model is developed to predict the internal behavior of power transistors operating under steady-state conditions. This model includes the internal self-heating effects in power transistors and is applicable to predict the transistor behavior under high-current and high-voltage operating conditions. The complete set of partial differential equations governing the bipolar semiconductor device behavior under nonisothermal conditions is solved by numerical techniques without assuming internal junctions and other conventional approximations. Input parameters for this model are the dimension of the device, doping profile, mobility expressions, generation-recombination model, and the boundary conditions for external contacts. Computer results of the analysis of a typical power transistor design are presented for specified operating conditions. The current density, electrostatic potential, carrier charge density, and temperature distribution plots within the transistor structure illustrate the combined effect of the electrothermal interaction, base conductivity modulation, current crowding, base pushout, space charge layer widening, and current spreading phenomena in power transistors.     

Thermal switchback in high ftepitaxial transistors

To investigate the reasons for second breakdown¹- or thermal switchback--and then to extend the safe operating area of power transistors, the behavior of an array of twenty small devices, mounted in parallel on a common heat sink, first without, then with an emitter series resistance, was evaluated. The first configuration suffers from β changes occurring at relatively low currents, an abrupt decrease of the base-to-emitter voltage, and failure to dissipate power. The configuration with emitter resistance shows a very tight collector-current base-current distribution, and normal base-to-emitter voltage characteristic. The same effect was obtained on a single large area device by employing a distributed thin-film resistor in series with the emitter. The uniform current distribution and the better thermal spreading of the heavily inter-digitated epitaxial device compensate for the small increase in saturation voltages due to the emitter resistance. Improved operating current levels and safe operating area are results observed on relatively small chip sizes.     

Experimental investigation of discrete air cooled device thermal resistance dependence on cooling conditions

Temperature is an important factor influencing the operation of electronic devices, thus adequate thermal models should be used for their accurate simulations. Unfortunately, the information on device thermal characteristics provided by their manufacturers is very scarce and usually it is limited only to the specification of the junction-to-case thermal resistance, which is not sufficient for the prediction of device dynamic thermal behaviour.This problem is discussed here based on the practical example of an air cooled power device operating at different power dissipation levels and in variable cooling conditions. The experiments presented in this paper demonstrate that the notion of junction-to-case thermal resistance is ambiguous since the cooling conditions affect the heat diffusion processes inside the package and consequently influence the thermal resistance value. For the analysed device, a simple four-stage RC Foster ladder model is proposed here to simulate the device dynamic thermal behaviour. Owing to the fact that this model is generated in a structure preserving way, its element values can be assigned some physical meaning.     

LED筒灯复合结构热管散热器的数值模拟

为解决LED筒灯使用单纯自然对流散热扩散热阻过大、温度分布不均的问题,提出一种基于平板热管和热虹吸管的复合结构热管散热器,并用数值模拟的方法研究了热功率、翅片高度、翅片数目、辐射换热对该散热器性能的影响。模拟结果表明应用于LED筒灯的复合结构热管散热器的热阻随着热功率的增加而减小,翅片高度和翅片数目存在一个最优值,使得散热器温度和热阻最小,自然对流情况下不可忽视辐射换热的作用。     

Physical study of the dissipated power area in high electron mobility transistors for thermal modelling

The hot area in power transistors due to the power dissipation is determined from a 2D-hydrodynamic model. The power is calculated everywhere in the device from the knowledge of the physical quantities (current density, electric field). The hot area is determined accurately to be coupled to a thermal modelling giving the temperature everywhere in the device [J. Park, M.-W Shin, C.-C. Lee, Thermal modeling and measurement of GaN-based HFET devices, IEEE Electron Device Lett. 24(7) (2003) 424-426 [1]; J.-C Jacquet, R. Aubry, H. Gérard, E. Delos, N. Rolland, Y. Cordier, A. Bussutil, M. Rousseau, S.L. Delage, Analytical transport model of AlGaN/GaN HEMT based on electrical and thermal measurement, 12th GAAS Symposium, Amsterdam, 2004, pp. 235-238 [2].]. The method is applied to HEMTs (high electron mobility transistors) based on GaAs or GaN. It is shown that the hot area depends on the bias conditions and on the transistor gate recess topology.     

Measurement of junction temperature of an AlGaAs/GaAsheterojunction bipolar transistor operating at large powerdensities

An electrical method to determine the junction temperature of a power bipolar transistor is presented. The success of this method does not rely on the constancy of thermal resistance over the wide range of operating temperatures. It is hence suitable for transistors operating at high power densities where conventional measurement techniques would not apply. Using this method, we establish that the junction temperature can be 40°C higher than the product of the low temperature thermal resistance and the power dissipation     

Non-linear thermal modeling of DMOS transistor and validation using electrical measurements and FEM simulations

The relevance of thermally non-linear silicon material models for transient thermal FEM simulations of smart power switches (SPS) is proved by a power silicon test device consisting of two power transistors and eleven integrated temperature sensors distributed over the silicon die. The test device is heated up by turning on an integrated power transistor in short-circuit for several milliseconds at two different initial temperatures. These thermal events correspond to a real situation that can occur in the application. The power dissipation in the power transistor is calculated from the measured source current and drain-source voltage, and subsequently used as an input to the FEM simulation. The temperature change on the test chip is measured by the integrated temperature sensors. An FEM model of the test chip encapsulated in a plastic package has been built in the FlexPDE simulator. The emphasis is put on the macroscopic modeling of the power transistor where an electro-thermal approach is reduced to a purely thermal one. Finally, the thermal events are simulated using FEM and compared to the temperature measurements. The results have shown that our modeling approach including non-linear properties of silicon can be used to investigate the thermal transients in SPS devices with high accuracy.     

Power dissipation calculation of the base spreading and contact resistance of transistors at low currents and low frequencies

The base spreading resistance of transistors is examined by the power dissipation method at low currents and low frequencies using analytical approximations and computer simulations. Results indicate that because of geometrical considerations the resistance values are reduced by a factor FR, which decreases with increasing aspect ratio. The results also show that for a rectangular-shaped intrinsic base region, when surrounded by an extrinsic one having negligible resistivity, FRvaries between 12 and 29 for an aspect ratio of infinity and 1:1, respectively. It is further shown that when the extrinsic region resistivity is accounted for, FRdecreases further as the extrinsic to intrinsic base sheet resistivity ratio increases. For completeness, the contact resistance expression is also derived with the power dissipation method, and it is shown to agree with that obtained using the transmission line approach. This method, therefore, is suited for the calculation of the total equivalent base resistance of a transistor.     

Theoretical analysis of modulation response and second-orderharmonic distortion in vertical-cavity surface-emitting lasers

A rate-equation model is developed, with the consideration of size effects, to analyze the steady state and dynamic behavior of index-guided vertical-cavity surface-emitting lasers. The size dependence of spatial hole burning, cavity loss, as well as thermal resistance of device cavity are taken into account. Using this model, the influence of size effects on the amplitude modulation response and second-order harmonic distortion are studied. It is found that a laser with a small core radius exhibits better modulation response and less harmonic distortion than that of a large waveguide device, however, there is a tradeoff between the output power and modulation efficiency of the lasers     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Electrothermal characterization of silicon-on-glass VDMOSFETs

Electrothermal consequences of implementing bulk-silicon RF power MOS processes in the silicon-on-glass substrate transfer technology are investigated in this paper. Fabricated silicon-on-glass vertical double-diffused MOSFETs are measured on-wafer and very large thermal resistance values are extracted for each design. The influence of the thermal resistance on RF performance is analyzed, and it is shown that strong electrothermal feedback severely lowers the power capability and strongly increases the operating temperature. A combination of low-thermal contacting and surface mounting to thermally conducting printed circuit board is shown to be very efficient in reducing the large thermal resistance. Numerical thermal simulations demonstrate that surface-mounted silicon-on-glass transistors can have lower thermal resistance than the bulk-silicon device with a wafer thickness reduced down to 100 μm.     

Transistor design and thermal stability

A model has been developed for the computation of forward second breakdown due to lateral thermal instability in power transistors. The method of analysis is to derive the steady-state current density and temperature distribution of a given transistor design under specified operating conditions, and then to calculate the response of the device to a temperature impulse suddenly applied internally. The current flow calculations have been carried out by using a distributed transistor model, and for the time-dependent heat flow problem the finite difference approach was used. The effect of device design parameters such as chip thickness, base width, emitter width, base impurity concentration, etc., on the thermal stability has been calculated. Also, the effect on transistor stability of the current and voltage operating point, as well as the heat sink temperature, has been analyzed. Information on the stability of a power transistor under pulsed condition is derived by calculating the time constant for thermal runaway. The results of this analysis indicate that the delay time is of the order of 1 ms.     

Modeling thermal effects on MOS I-V characteristics

The temperature distribution in a MOS transistor caused by power dissipation within the device has been calculated by solving the heat diffusion equation. Using this temperature distribution, IV characteristics of a MOS device as modified by thermal effects are calculated. The predicted behavior matches reported experimental observations; in particular, the negative dynamic resistance seen in the saturation region of devices operating at elevated power densities.