A Monte Carlo approach for power estimation

The authors investigate a power estimation technique for VLSI that combines the accuracy of simulation-based techniques with the speed of the probabilistic techniques. The resulting method is statistical in nature; it consists of applying randomly generated input patterns to the circuit and monitoring, with a simulator, the resulting power value. This is continued until a value of power is obtained with a desired accuracy, at a specified confidence level. The authors present the algorithm and experimental results, and discuss the superiority of the approach     

Nonlinear statistical modeling and yield estimation technique foruse in Monte Carlo simulations [microwave devices and ICs]

A novel nonlinear statistical modeling technique for microwave devices and a new approach to yield estimation for microwave integrated circuits are presented. The statistical modeling methodology is based on a combination of applied multivariate methods with heuristic techniques. These include principal component analysis and factor analysis in conjunction with maximally flat quadratic interpolation and group method of data handling. The proposed modeling approach, when applied to the database of extracted equivalent circuit parameters (ECPs) for a pseudomorphic high electron mobility transistor device, has proven that it can generate simulated ECPs, S-parameters, that are statistically indistinguishable from measured ones. A new yield estimation technique based on a Latin hypercube sampling (LHS) is also demonstrated. The LHS-based simulation is utilized as an alternative to primitive Monte Carlo (PMC) simulation in yield analysis. An equally confident yield estimate based on the LHS method requires only one-fourth of those simulations needed when the PMC technique is used     

Improving power efficiency of CSMA wireless networks using multi-user diversity - [transaction letters]

This paper proposes a method that reduces transmit-power consumption of carrier-sense multiple-access (CSMA) networks by utilizing multi-user diversity and power control. Using this method, a terminal sends a packet at a slot if the terminal?s signal-to-noise ratio (SNR) is above the threshold associated with the slot. Since the threshold value decreases as time advances, this method will make the user with the largest SNR access the shared channel; thus, a packet can be transmitted with less transmit power. The analysis under the infinite-user model shows that, as traffic load grows, the expected sum-power of the conventional CSMA network increases whereas that of the proposed method decreases.     

Peak power estimation of VLSI circuits: new peak power measures

New measures of peak power are proposed in the context of sequential circuits, and an efficient automatic procedure is presented to obtain very good lower bounds on these measures, as well as providing the actual input vectors that attain such bounds. Automatic generation of a functional vector loop for near-worst case power consumption is also attained. Experiments show that vector sequences generated give much more accurate estimates of peak power dissipation and are generated in significantly shorter execution times than estimates made from randomly generated sequences for four delay models     

Component placement in VLSI circuits using a constant pressure Monte Carlo method

When laying out a VLSI circuit on a silicon wafer the object is to pack the components of the circuit onto a wafer of minimum area subject to a variety of conflicting constraints associated with electrical interconnections among the components and input/ output connections. A constant pressure Monte Carlo method is applied to an idealized component placement problem where the object is to pack different rectangular components onto a square of minimum area with a subsidiary objective of minimizing the total length of wires interconnecting the components. The Monte Carlo method is found to be remarkably effective in solving this idealized problem. No other method for solving this problem is known.     

Efficient algorithms for multilevel power estimation of VLSI circuits

This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS technologies with an accuracy that is comparable to a SPICE simulation but up to 10 000 times faster. The outlined approach is capable of handling complex circuits consisting of more than 20 000 cells and thousands of memory elements. Very large sets of input data with several millions of patterns can, thus, be simulated in an efficient way. This allows the prediction of mean power dissipation of VLSI circuits in a realistic functional context which provides new assessment possibilities for digital CMOS low-power design methods. Experimental results for some benchmark circuits are detailed in order to demonstrate the significant improvements in terms of performance, accuracy, and flexibility of this approach compared to state-of-the-art power estimation methods     

A survey of power estimation techniques in VLSI circuits

With the advent of portable and high-density microelectronic devices, the power dissipation of very large scale integrated (VLSI) circuits is becoming a critical concern. Accurate and efficient power estimation during the design phase is required in order to meet the power specifications without a costly redesign process. In this paper, we present a review of the power estimation techniques that have recently been proposed     

Two-dimensional retiming [VLSI design]

This paper considers two-dimensional (2-D) retiming, which is the problem of retiming circuits that operate on 2-D signals. We begin by discussing two types of parallelism available in 2-D data processing, which we call inter-iteration parallelism and inter-operation parallelism. We then present two novel techniques for 2-D retiming that can be used to extract inter-operation parallelism. These two techniques are designed to minimize the amount of memory required to implement a 2-D data-flow graph while maintaining a desired clock rate for the circuit. The first technique is based on an integer linear programming (ILP) formulation of the problem, and is called ILP 2-D retiming. This technique considers the entire 2-D retiming problem as a whole, but long central processing unit times are required if the circuit is large. The second technique, called orthogonal 2-D retiming, is a linear programming formulation which is derived by partitioning ILP 2-D retiming into two parts called s- and a-retiming. This technique finds a solution in polynomial time and is much faster than the ILP 2-D retiming technique, but the two sub problems (s- and a-retiming) can give results which are not compatible with one another. To solve this incompatibility problem, a variation of orthogonal 2-D retiming called integer orthogonal 2-D retiming is developed. This technique runs in polynomial time and the s-retiming and a-retiming steps are guaranteed to give compatible results. We show that the techniques presented in this paper can result in memory hardware savings of 50% compared to previously published 2-D retiming techniques     

Time-varying ARMA stable process estimation using sequential Monte Carlo

Various time series data in applications ranging from telecommunications to financial analysis and from geophysical signals to biological signals exhibit non-stationary and non-Gaussian characteristics. α-Stable distributions have been popular models for data with impulsive and non-symmetric characteristics. In this work, we present time-varying autoregressive moving-average α-stable processes as a potential model for a wide range of data, and we propose a method for tracking the time-varying parameters of the process with α-stable distribution. The technique is based on sequential Monte Carlo, which has assumed a wide popularity in various applications where the data or the system is non-stationary and non-Gaussian.     

Reduction of power consumption during test application by testvector ordering [VLSI circuits]

The authors address the problem of testing VLSI circuits without exceeding their power ratings during testing. The proposed approach is based on re-ordering test vectors in a test sequence to minimise the switching activity of the circuit during test application. Results or experiments are presented which show a power reduction in the range 7.5-55.8% during test application     

Maximum likelihood parameter estimation of superimposed chirpsusing Monte Carlo importance sampling

We address the problem of parameter estimation of superimposed chirp signals in noise. The approach used here is a computationally modest implementation of a maximum likelihood (ML) technique. The ML technique for estimating the complex amplitudes, chirping rates, and frequencies reduces to a separable optimization problem where the chirping rates and frequencies are determined by maximizing a compressed likelihood function that is a function of only the chirping rates and frequencies. Since the compressed likelihood function is multidimensional, its maximization via a grid search is impractical. We propose a noniterative maximization of the compressed likelihood function using importance sampling. Simulation results are presented for a scenario involving closely spaced parameters for the individual signals     

Silhouette-based human pose estimation using reversible jump Markov chain Monte Carlo

A novel approach for recovering the human body configuration based on the silhouette is presented. By considering pose inference as traversing the difference subspaces and using a data-driven mechanism, reversible jump Markov chain Monte Carlo (RJMCMC) can explore such solution space very efficiently. Experimental results are provided to demonstrate the efficiency and effectiveness of the proposed approach.     

Monte Carlo estimation of hot carrier noise at millimeter- and submillimeter-wave frequencies

This paper deals with the use of Monte Carlo experiments for investigating noise phenomena associated with hot carrier transport in semiconductors. In the first part of the paper procedures and problems associated with the design and interpretation of such experiments are discussed. The use of a Monte Carlo experiment is then demonstrated by estimating the velocity fluctuation spectrum of electrons in GaAs. Significant new results and insights are obtained. In particular, two new Spectral peaks are discovered and explained in terms of underlying physical processes, certain simple intuitive assumptions often made in noise theory are shown to be unjustified, and a criterion for the minimum flight time needed for estimates of "conventional" diffusion coefficients is obtained.     

Regional Monte Carlo modeling of electron transport andtransit-time estimation in graded-base HBT's

Steady-state electron transport in graded-base heterojunction bipolar transistors is investigated using a regional ensemble Monte Carlo approach. Besides the graded band and scattering parameters already incorporated in the particle model, emitter-base and collector-base junctions are also considered in the boundary conditions for carrier injection/absorption. It is shown that optimum base transit times are directly related to the maximum average velocities, which occur at different base width-composition combinations. It also illustrates a general approach to studying electron transport in graded-band devices     

低压电力线信道建模与蒙特卡洛模拟

在分析均匀传输线信道特性的基础上,引入二端口网络理论,分析低压电力线带负载信道的传输特性。采用二端口网络理论的T参数传输矩阵建立了低压电力线信道传输模型,然后利用蒙特卡洛方法建立仿真模型。模型从不同负载特性、不同接入或撤出负载变化量、不同传输信号频率对信号的影响分别进行了仿真和分析。仿真结果表明,采用二端口网络理论建立起的信道模型是可行的;采用蒙特卡洛数值模拟方法模拟低压电力线带负载信道是除了实际测试信道之外又一个可以借鉴的方法。