Fabrication and program/erase characteristics of 30-nm SONOS nonvolatile memory devices

In this paper, we have fabricated nanoscale silicon-oxide-nitride-oxide-silicon (SONOS) nonvolatile memory devices by means of the sidewall patterning technique. The fabricated SONOS devices have a 30-nm-long and 30-nm-wide channel with 2.3/12/4.5-nm-thick oxide/nitride/oxide film on fully depleted-silicon-on-insulator (FD-SOI) substrate. The short channel effect is well suppressed though devices have very short channel length and width. Also, the fabricated SONOS devices guarantee good retention and endurance characteristics. In 30-nm SONOS devices, channel hot electron injection program mechanism is inefficient and 2-b operation based on localized carrier trapping in the nitride film is difficult. The erase speed is improved by means of band-to-band (BTB) assisted hole injection mechanism. In 30-nm SONOS devices, program and erase operation can be performed efficiently with improved erase speed by combination of Fowler-Nordheim (F-N) tunneling program and BTB assisted hole injection erase mechanism because the entire channel region programmed by F-N tunneling can be covered by two-sided hole injection from source and drain.     

A Vertical 4-Bit SONOS Flash Memory and a Unique 3-D Vertical nor Array Structure

In order to overcome the limitation of a multibit silicon–oxide–nitride–oxide–silicon (SONOS) memory with multistorage nodes, we propose a unique 3-D vertical nor (U3VNOR) array architecture. The U3VNOR has a vertical channel so that it is possible to have a long enough channel without extra cell area. Therefore, we can avoid the problems such as redistribution of injected charges, second-bit effect, and short-channel effect. Also, it is the most integrated flash architecture having the smallest unit cell size, which is 1 $hbox{F}^{2}!hbox{/}hbox{bit}$. In this paper, we present the fabrication method and the operation voltage scheme of the U3VNOR. In addition, through numerical simulation, we verify its program and erase characteristics. Due to its high density and reliable multibit operation, the U3VNOR is a promising structure for the future high-density nor flash memory.      

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon devices with a separated double-gate saddle-type structure

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon flash memory devices based on a separated double-gate (SDG) saddle structure with a recess channel region had two different doping regions in silicon-fin channel to operate two-bit per cell. A simulation results showed that the short channel effect, the cross-talk problem between cells, and the increase in threshold voltage distribution were minimized, resulting in the enhancement of the scaling-down characteristics and the program/erase speed.     

Electrical characteristics of nanoscale NAND silicon-oxide-nitride-oxide-silicon flash memory devices fabricated on SOI substrates

NAND silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with double gates fabricated on silicon-on-insulator (SOI) substrates were proposed. The current-voltage characteristics related to the programming operation of the designed nanoscale NAND SONOS flash memory devices on a SOI substrate and on the conventional bulk-Si substrate were simulated and compared in order to investigate device characteristics of the scaled-down memory devices. The simulation results showed that the short channel effect and the subthreshod leakage current for the memory device with a large spacer length were lower than that of the memory device with a small spacer length due to increase of the effective channel length. The device performance of the memory device utilizing the SOI substrate exhibited a smaller subthreshold swing and a larger drain current level in comparison with those on the bulk-Si substrate. These improved electrical characteristices for the SOI devices could be explained by comparing the electric field distribution in a channel region for both devices.     

High-performance bottom-gate poly-Si polysilicon-oxide-nitride-oxide-silicon thin film transistors crystallized by excimer laser irradiation for two-bit nonvolatile memory applications

High-performance bottom-gate (BG) poly-Si polysilicon-oxide-nitride-oxide-silicon (SONOS) TFTs with single grain boundary perpendicular to the channel direction have been demonstrated via simple excimer-laser-crystallization (ELC) method. Under an appropriate laser irradiation energy density, the silicon grain growth started from the thicker sidewalls intrinsically caused by the bottom-gate structure and impinged in the center of the channel. Therefore, the proposed ELC BG SONOS TFTs exhibited superior transistor characteristics than the conventional solid-phase-crystallized ones, such as higher field effect mobility of 393 cm2/V-s and steeper subthreshold swing of 0.296 V/dec. Due to the high field effect mobility, the electron velocity, impact ionization, and conduction current density could be enhanced effectively, thus improving the memory performance. Based on this mobility-enhanced scheme, the proposed ELC BG SONOS TFTs exhibited better performance in terms of relatively large memory window, high program/erase speed, long retention time, and 2-bit operation. Such an ELC BG SONOS TFT with single-grain boundary in the channel is compatible with the conventional a-Si TFT process and therefore very promising for the embedded memory in the system-on-panel applications.     

Twin-bit silicon-oxide-nitride-oxide-silicon (SONOS) memory by inverted sidewall patterning (TSM-ISP)

We have proposed a new twin-bit silicon-oxide-nitride-oxide-silicon memory (TSM)-inverted sidewall patterning (ISP) cell which has twin oxide-nitride-oxides (ONOs) physically separated by the ISP method under one control gate. This TSM-ISP can control the trapped charge distribution and make diffusion barrier of charges, so that program/erase (P/E) endurance and retention can be increased. The trapping nitride is narrow enough to reduce hot-hole erase times. To estimate the new device characteristics, we have devised a special simulation method of silicon-oxide-nitride-oxide-silicon (SONOS) by implementing a simple idea in the conventional device simulator, "MEDICI." By placing the floating nodes in nitride with adjusted density, which is supposed to play the role of charge traps in nitride, we can estimate not only the conventional SONOS characteristics, but also the new SONOS characteristics, such as TSM-ISP.     

Nanoscale two-bit/cell NAND silicon-oxide-nitride-oxide-silicon memory device with different tunneling oxide thicknesses

Nanoscale two-bit/cell NAND-type silicon-oxide-nitride-oxide-silicon (SONOS) flash memory devices with different tunneling oxide thicknesses were designed to reduce the short channel effect and the coupling interference. The process step and the electrical characteristics of the proposed SONOS memory devices were simulated by using SUPREM-4 and MEDICI, respectively. The short channel effect in the nanoscale two-bit/cell SONOS devices was decreased than that of the conventional devices due to a larger effective channel length. The drain current at the on-state of the proposed NAND SONOS memory devices decreased than that of the conventional NAND SONOS devices due to the high channel resistivity. The I on/I off ratio of the proposed NAND SONOS memory devices was larger than that of the conventional memory devices due to the dramatic decrease in the subthreshold current of the proposed devices. The electrical characteristics of the NAND SONOS memory devices with different tunneling oxide thicknesses were better than those of the conventional NAND SONOS devices.     

Depletion-enhanced body-isolation (DEBI) array on SOI for highly scalable and reliable NAND flash memories

A novel array architecture [depletion-enhanced body-isolation (DEBI)] has been proposed for NAND-type flash memories, and its memory characteristics are investigated in detail by device simulations. Having the shallow junctions on the thin active area, the proposed array architecture achieves high device performances with a fully depleted silicon-on-insulator (FDSOI) structure and enables stable erase operation without any problems based on an SOI structure. In particular, during the program operation, the DEBI architecture exhibited excellent self-boost efficiency originating from the isolated body. This can reduce the program disturbance effectively and can lower the V/sub pass/ voltages.     

多晶硅/氧化硅/多晶硅非平面结构中Fowler-Nordheim隧穿及氧化层退化研究(英文)

Fowler-Nordheim隧穿被广泛应用于EEPROM和闪存中的擦除操作。多晶硅到多晶硅的F-N隧穿具有较高的隧穿效率。本论文基于分栅闪存存储器的结构,对于多晶硅/隧穿氧化层/多晶硅非平面结构的F-N隧穿及其引起的氧化层退化进行了研究。相比于平面结构,非平面结构显示出更高的F-N隧穿效率,且隧穿效率还可通过降低氧化层厚度或者增加预热氧化处理的方法进一步提高。较低的F-N隧穿电流密度显示出较慢的隧穿氧化层退化速率。降低氧化层厚度或者增加热氧化处理也可减缓隧穿氧化层的退化。另外,论文还讨论了研究结果对于改善分栅闪存擦除特性以及耐久性的意义。     

Effects of tunnel oxide process on SONOS flash memory characteristics

In this paper, various process conditions of tunnel oxides are applied in SONOS flash memory to investigate their effects on charge transport during the program/erase operations. We focus the key point of analysis on Fermi-level (E_F) variation at the interface of silicon substrate and tunnel oxide. The Si-O chemical bonding information which describes the interface oxidation states at the Si/SiO₂ is obtained by the core-level X-ray photoelectron spectroscopy (XPS). Moreover, relative E_F position is determined by measuring the Si 2p energy shift from XPS spectrums. Experimental results from memory characteristic measurement show that MTO tunnel oxide structure exhibits faster erase speed, and larger memory window during P/E cycle compared to FTO and RTO tunnel oxide structures. Finally, we examine long-term charge retention characteristic and find that the memory windows of all the capacitors remain wider than 2 V after 10⁵ s.     

Comparative analysis of trap-based program/erase behaviors with different tunnel barriers

In this study, we comparatively analyze the trap-based memory characteristics of Oxide-Nitride-Oxide (ONO) devices with different tunnel dielectrics. We fabricated two kinds of ONO devices-one is the conventional single tunnel oxide structure and the other is the bandgap engineered structure in which the modulated tunnel dielectric replaces the single tunnel oxide. The charge storage layer is 9 nm and the blocking oxide is 7 nm in both two kinds of ONO devices. Based on experimental results, we find that the memory speed is promoted to 2-4 times and 10-year data retention greatly improves in the bandgap engineered device comparing to those in the conventional device. As a result, the bandgap engineered tunnel barrier device embodies both fast P/E operation speeds and excellent long-term data retention characteristics, hence, the bandgap engineered tunnel barrier is expected to conduct performance optimization for the future scaled SONOS flash memory.     

Extremely scaled 3-dimensional multiple-gate technologies for terabit era

In order to make possible silicon-based, room-temperature operable devices having a feature size in the sub-5 nm range, an all-around gate FinFET having an extremely narrow gate-surrounded silicon fin with a floating body was proposed and fabricated. Sub-10 nm device issues such as short channel effects, punchthrough, source/drain series resistance, gate misalignment, and hot-carrier injection were intensively studied and optimized for the sub-5 nm structure. The sub-5 nm all-around gate FinFET with 3 nm fin width and 1.2 nm EOT was demonstrated for the first time.     

Fabrication, characterization and simulation of high performance Si nanowire-based non-volatile memory cells

We report the fabrication, characterization and simulation of Si nanowire SONOS-like non-volatile memory with HfO(2) charge trapping layers of varying thicknesses. The memory cells, which are fabricated by self-aligning in situ grown Si nanowires, exhibit high performance, i.e. fast program/erase operations, long retention time and good endurance. The effect of the trapping layer thickness of the nanowire memory cells has been experimentally measured and studied by simulation. As the thickness of HfO(2) increases from 5 to 30 nm, the charge trap density increases as expected, while the program/erase speed and retention remain the same. These data indicate that the electric field across the tunneling oxide is not affected by HfO(2) thickness, which is in good agreement with simulation results. Our work also shows that the Omega gate structure improves the program speed and retention time for memory applications.     

Non-volatile flash memory with discrete bionanodot floating gate assembled by protein template

We demonstrated non-volatile flash memory fabrication by utilizing uniformly sized cobalt oxide (Co(3)O(4)) bionanodot (Co-BND) architecture assembled by a cage-shaped supramolecular protein template. A fabricated high-density Co-BND array was buried in a metal-oxide-semiconductor field-effect-transistor (MOSFET) structure to use as the charge storage node of a floating nanodot gate memory. We observed a clockwise hysteresis in the drain current-gate voltage characteristics of fabricated BND-embedded MOSFETs. Observed hysteresis obviously indicates a memory operation of Co-BND-embedded MOSFETs due to the charge confinement in the embedded BND and successful functioning of embedded BNDs as the charge storage nodes of the non-volatile flash memory. Fabricated Co-BND-embedded MOSFETs showed good memory properties such as wide memory windows, long charge retention and high tolerance to repeated write/erase operations. A new pathway for device fabrication by utilizing the versatile functionality of biomolecules is presented.     

Scaling considerations for sub-90 nm split-gate flash

A systematic methodology is presented to scale split-gate (SG) flash memory cells in the sub-90 nm regime within the presently known scaling constraints of flash memory. The numerical device simulation results show that the high performance sub-90 nm NOR-type SG cells can be achieved by a suitable channel and source-drain engineering. An asymmetric channel doping profile along with ultra-shallow source-drain junctions was used to achieve the target drain programming voltage (V_sp) for an efficient cell programming while keeping the cell breakdown voltage, BV > V_sp, with tolerable leakage currents. The study shows that with properly optimised technology parameters, 65 nm SG-NOR flash memory can be achieved with an adequate cell read current, a tolerable programmed cell leakage current at the read condition and efficient write and erase times.     

Memory characteristics of Al<Subscript>2</Subscript>O<Subscript>3</Subscript>/LaAlO<Subscript>3</Subscript>/SiO<Subscript>2</Subscript> multilayer structures with tunnel oxide thickness variation

Charge trap flash (CTF) memory devices are candidates to replace NAND flash devices. In this study, Pt/Al₂O₃/LaAlO₃/SiO₂/Si multilayer structures with lanthanum aluminate charge traps were fabricated for nonvolatile memory device applications. An aluminum oxide film was used as a blocking oxide for low power consumption in the program/erase operation and to minimize charge transport through the blocking oxide layer. The thickness of SiO₂ as tunnel oxide layer was varied from 30 to 50 Å. Thicknesses of oxide layers were confirmed by high resolution transmission electron microscopy (HRTEM) and all the samples showed amorphous structure. From the C–V measurement, a maximum memory window of 3.4 V was observed when tunnel oxide thickness was 40 Å. In the cycling test for reliability, the 30 Å tunnel oxide sample showed a relatively large memory window reduction by repeated program/erase operations due to the high electric field of ~10 MV/cm through tunnel oxide. The other samples showed less than 10% loss of memory window during 10⁴ cycles.     

Charge trapping devices using a bilayer oxide structure

This experiment is the first exploration of use of charge traps in the bulk of deposited top oxide and at the interface between thermal oxide and deposited top oxide. We report the operational characteristics of SiO2/SiO2 device structures with 0.5 microm gate width and length. Low power operations are achieved through very thin gate stacks of 3 nm of thermally grown oxide and 7 nm of deposited oxide. However, narrow memory windows have been acquired comparing with conventional silicon-oxide-nitride-oxide-silicon (SONOS) memory cells due to a low trap density at the interface between a grown oxide and a deposited oxide. Additionally, the electric field between the channel and the charge is determined by solving 1D Poisson equation at a given write voltage, then total tunneling current density is calculated to make a program modeling for charge trapping devices. Tunneling/trapping simulation based on Fowler-Nordheim (F-N) tunneling performed and it fits the programming curves well. The memory window is almost constant after 100,000 cycles, and the retention characteristics are deteriorated rapidly.     

Memory effect of low-temperature processed ZnO thin-film transistors having metallic nanoparticles as charge trapping elements

In this study, non-volatile memory effect was characterized using the single-transistor-based memory devices based on self-assembled gold nanoparticles (AuNP) as the charge trapping elements and atomic-layer deposited ZnO as the channel layer. The fabricated memory devices showed controllable and reliable threshold voltage shifts according to the program/erase operations that resulted from the charging/discharging of charge carriers in the charge trapping elements. Reliable non-volatile memory properties were also confirmed by the endurance and data retention measurements. The low temperature processes of the key device elements, i.e., AuNP charge trapping layer and ZnO channel layer, enable the use of this device structure to the transparent/flexible non-volatile memory applications in the near future.     

Electrical characteristics of FinFET with vertically nonuniform source/drain doping profile

The effects of a nonuniform source/drain (S/D) doping profile on the FinFET characteristics are investigated using three-dimensional device simulation. With a fixed S/D doping profile, larger silicon-on-insulator (SOI) thickness can suppress short-channel effects due to the coexistence of longer channel regions. There can be some design margin in the channel thickness due to this reduced short-channel effect. Drain saturation current in FinFET is proportional to the effective device width and SOI thickness. To determine the appropriate SOI thickness of FinFET, alternating current (AC) characteristics are investigated. Device capacitance increases with SOI thickness, but this is not for the gate delay, as the drive current also increases and compensates for the increase of capacitance. When driving a constant capacitance load such as interconnect, devices with larger drain current or thicker SOI are more favorable for the fixed S/D doping condition.     

Detection of charge storage on molecular thin films of tris(8-hydroxyquinoline) aluminum (Alq3) by Kelvin force microscopy: a candidate system for high storage capacity memory cells

Retention and diffusion of charge in tris(8-hydroxyquinoline) aluminum (Alq(3)) molecular thin films are investigated by injecting electrons and holes via a biased conductive atomic force microscopy tip into the Alq(3) films. After the charge injection, Kelvin force microscopy measurements reveal minimal changes with time in the spatial extent of the trapped charge domains within Alq(3) films, even for high hole and electron densities of >10(12) cm(-2). We show that this finding is consistent with the very low mobility of charge carriers in Alq(3) thin films (<10(-7) cm(2)/(Vs)) and that it can benefit from the use of Alq(3) films as nanosegmented floating gates in flash memory cells. Memory capacitors using Alq(3) molecules as the floating gate are fabricated and measured, showing durability over more than 10(4) program/erase cycles and the hysteresis window of up to 7.8 V, corresponding to stored charge densities as high as 5.4 × 10(13) cm(-2). These results demonstrate the potential for use of molecular films in high storage capacity nonvolatile memory cells.