基于片内总线的系统芯片（SoC）硬件调试器

本文提出基于SoC片内总线的嵌入式硬件调试器的设计方法,提高了调试速度和通用性,使SoC用户通过简单的标准串口就能够暂停内都微处理器的指令流水线,快速地访问微处理器内部的寄存器、外部的存储单元,监视内部的指令执行情况和片内总线的数据传输情况。     

高效能,低功耗DDR2控制器的硬件实现

随着SoC芯片内部总线带宽的需求增加,内存控制器的吞吐性能受到诸多挑战。针对提升带宽性能的问题,可以从两个方面考虑,一个办法是将内存控制器直接跟芯片内部几个主要占用带宽的模块连接,还要能够对多个通道进行智能仲裁,让他们的沟通不必经过内部的AMBA总线,甚至设计者可以利用高效能的AXI总线来加快SoC的模块之间的数据传输。另一个办法就是分析DDR2SDRAM的特性后设计出带有命令调度能力的控制器来减少读写次数,自然就能够降低SoC芯片的功耗,为了节能的考虑还要设计自动省电机制。本文为研究DDR2SDRAM控制器性能的提升提供良好的思路。     

MCS-DMA：一种面向SoC内DMA传输的内存控制器优化设计

当前主流片上总线协议—AHB存在访存带宽利用率较低的问题.本文基于SoC内DMA传输较多的特点,提出一种新的优化设计：在内存控制器内部增加MCS-DMA模块,并通过驱动程序将MCS-DMA模块与目标DMA传输绑定. 一方面实现数据预取,提升单个DMA传输时的总线带宽利用率;另一方面使访存请求在内存控制器内部流水化完成,提升多个DMA并发时的总线带宽利用率.将该设计应用到北大众志SK SoC后,单个DMA传输时的总线带宽利用率提升至100%,多个DMA并发时的总线带宽利用率从33.3%提升至85.5%,而芯片设计面积仅增加2.9%．     

基于SystemC的事务级建模研究

探讨了基于SystemC的事务级建模方法,并结合SoC片上总线,以DVB-C数字电视机顶盒给出建模实例.基于SystemC的SoC总线模型有效克服了SoC软硬件协同设计的时间瓶颈问题,提高了开发效率,缩短了产品的开发周期.目前该系统正处于板级调试过程中.     

低翻转率的SoC总线组合编码算法

为降低SoC总线功耗,避开现有总线编码技术在应用上的局限,提出了一种SoC总线编码算法。算法基于总线上IP可复用的观点,采用分组BI码和TO码各自的优点,在维持SoC总线功能基本不变的同时,减少数据线和地址线的电平翻转。最后的实验结果表明：组合编码算法可以将SoC总线的平均功耗下降7．41％,是一种有效且适用于SoC总线的低功耗算法。     

基于3G SIM卡SoC芯片设计的AMBA总线的精简策略

AMBA总线是SoC设计中普遍采用的总线架构,它对许多具体的设计项目往往显得过于庞大,结合3G SIM卡SoC芯片的设计,研究了AMBA总线架构的若干精简策略,提出了一些对总线进行裁剪的参考方法,经过AHB VIP验证环境表明结果可行.该方法对基于AMBA架构的SoC芯片设计有着一定的参考意义.     

SoC设计中的片上通信体系结构研究

以超深亚微米工艺和IP核复用技术为支撑的系统芯片(SoC)技术,是目前超大规模集成电路和嵌入式电子产品设计的主流.SoC中各IP核之间的片上通信体系结构是SoC设计关键技术之一,同时对SoC的性能起着至关重要的作用.提出一种SoC中的混合片上通信体系结构,该体系结构将传统的共享总线与片上网络相结合,既保留了片上共享总线面积小的优点,又具有片上网络的并行通信的优点.此外,该混合片上通信还可以扩展到二维网络.     

一款嵌入式芯片总线仲裁器的设计和评估

针对片上系统(SoC)总线设计中仲裁机制的选取往往局限于抽象的定性分析,以一款嵌入式处理器芯片为设计平台,实现了固定优先级、轮转优先级和混合优先级的仲裁电路设计,并建立了仿真测试平台,通过仿真对总线主设备的总线占有率、最差等待响应时间进行了定量分析比较,得出了混合优先级仲裁机制较单一的固定优先级与轮转优先级仲裁机制在体现公平性与优先性上更有效的结论,对其他嵌入式系统总线的仲裁设计与改进提供了很好的参考.     

一种基于JTAG的SoC片上调试系统的设计

基于SoC的硬件设计,提出了一种基于JTAG的SoC3片上调试系统的设计方法.该调试系统可设置多种工作模式,含有CPU核扫描链和片上总线扫描链.能硬件实现调试启动与停止、断点设置、单步执行及存储访问等调试功能.对外围IP模块调试诊断时,可绕开CPU核,通过片上总线扫描链直接进行读写访问.该调试系统对其他SoC的设计具有一定的参考价值.     

片上系统(SoC)的VoIP网关的研究

介绍了如何使用IP核复用技术进行SoC的开发,分析了VoIP网关的体系结构.在研究VoIP网关功能的基础之上,给出了SoC的VoIP网关的硬件布局和IP核的总线设计构架.     

Pipelined Scheduling of Functional HW/SW Modules for Platform‐Based SoC Design

We developed a pipelined scheduling technique of functional hardware and software modules for platform‐based system‐on‐a‐chip (SoC) designs. It is based on a modified list scheduling algorithm. We used the pipelined scheduling technique for a performance analysis of an MPEG4 video encoder application. Then, we applied it for architecture exploration to achieve a better performance. In our experiments, the modified SoC platform with 6 pipelines for the 32‐bit dual layer architecture shows a 118% improvement in performance compared to the given basic SoC platform with 4 pipelines for the 16‐bit single‐layer architecture.     

基于LEON2处理器的SoC设计

SoC已逐渐成为集成电路设计的主流发展趋势,而其中的微处理器部分尤为重要.选用LEON2处理器核,是一款可合成的VHDL模型,是基于SPARC V8结构的32位处理器,具有高度的可配置性,尤其适用于SoC设计,设计者可为其特定应用选择不同的外围设备IP核.本文介绍了LEON2处理器核的基本特征及其外围设备的IP核,主要讨论了基于LEON2处理器的SoC设计.     

Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication

The on-chip communication architecture is a primary determinant of overall performance in complex system-on-chip (SoC) designs. Since the communication requirements of SoC components can vary significantly over time, communication architectures that dynamically detect and adapt to such variations can substantially improve system performance. In this paper, we propose Flexbus, a new architecture that can efficiently adapt the logical connectivity of the communication architecture and the components connected to it. Flexbus achieves this by dynamically controlling both the communication architecture topology, as well as the mapping of SoC components to the communication architecture. This is achieved through new dynamic bridge by-pass, and component remapping techniques. In this paper, we introduce these techniques, describe how they can be realized within modern on-chip buses, and discuss policies for run-time reconfiguration of Flexbus-based architectures.      

基于国产自主CPU的SEP0611平台中Dalvik虚拟机的移植和优化

Dalvik是Google公司自己设计用于Android平台的Java虚拟机,Andriod系统不支持所有构架的特性使将andriod系统移植到基于国产内核Unity的Soc的SoC SEP0611上有着大量的工作.对Dalvik虚拟机平台相关性和无关性进行分析,使对虚拟机的移植有了基本认识和实现基础,同时介绍了我们自主研发的基于国产自主内核的SoC,将与基于国产内核Unity架构平台相关的JNI(Java Native Interface)机制进行分析,找到了移植的关键环节本地调用桥(Callbridge),同时对Dalvik虚拟机优化的进行了分析与研究,找到了解释器优化的最好途径,即用汇编重写解释器,并初步探讨了JIT( Just In Time)编译器的实现方法.通过实现本地调用桥,实现了Dalvik虚拟机在SEP0611国产自主SoC上的移植.     

FABSYN: floorplan-aware bus architecture synthesis

As system-on-chip (SoC) designs become more complex, it is becoming harder to design communication architectures to handle the ever increasing volumes of inter-component communication. Manual traversal of the vast communication design space to synthesize a communication architecture that meets performance requirements becomes infeasible. In this paper, we address this problem by proposing an automated approach for floorplan-aware bus architecture synthesis (FABSYN) to synthesize cost-effective, bus-based communication architectures that satisfy the performance constraints in a design. Our synthesis approach incorporates a high-level floorplanning and wire delay estimation engine to evaluate the feasibility of the synthesized bus architecture and detect bus cycle time violations early in the design How, at the system level. We present case studies of network communication SoC subsystems for which we synthesized bus architectures, detected and eliminated timing violations, and generated core placements in a matter of hours instead of several days for a manual effort.     

一种新型多媒体SoC验证平台原理及其实现

提出了一种基于ADSP-BF537的新型多媒体SoC验证平台,以满足多媒体SoC音视频编解码功能模块的实时验证。介绍了整个平台的基本组成,以及BF537与SoC接口的软硬件设计;最后,以验证用于SoC的MP3硬件解码器模块为例,讨论了如何利用BF537,在多媒体SoC的FPGA原型内进行软硬件协同验证。该验证方案已经成功应用在深圳艾科创新微电子有限公司的一款多媒体SoC设计流程中。     

Performance Analysis for MPEG‐4 Video Codec Based on On‐Chip Network

In this paper, we present a performance analysis for an MPEG‐4 video codec based on the on‐chip network communication architecture. The existing on‐chip buses of system‐on‐a‐chip (SoC) have some limitation on data traffic bandwidth since a large number of silicon IPs share the bus. An on‐chip network is introduced to solve the problem of on‐chip buses, in which the concept of a computer network is applied to the communication architecture of SoC. We compared the performance of the MPEG‐4 video codec based on the on‐chip network and Advanced Micro‐controller Bus Architecture (AMBA) on‐chip bus. Experimental results show that the performance of the MPEG‐4 video codec based on the on‐chip network is improved over 50% compared to the design based on a multi‐layer AMBA bus.     

基于SoC平台的H.264解码器IP核设计

介绍了SoC的发展概况和趋势,提出了一种基于SoC平台的H．264解码器优化设计架构。在设计中采取了灵活的帧场自适应解码策略,对于总线时序需求较高的模块采用了流水线设计,对总线进行了时分复用;在可变长解码部分．对各个功能模块进行了控制分离,这些优化除了可有效地减小时钟频率需求外,还可在一定程度上兼容其它的视额压缩标准．如MPEG-2。最后实现了这个设计,并给出了实验结果。     

SoC的存储器Wrapper设计及故障测试

在系统芯片SoC测试中,存储器的可靠性测试是一项非常重要内容.IEEE Std 1500是专门针对嵌入式芯核测试所制定的国际标准,规范了IP核提供者和使用者之间的标准接口.基于此标准完成针对SoC存储器的Wrapper测试壳结构和控制器的设计.以32×8的SRAM为测试对象进行测试验证.结果表明,系统能够准确的诊断出存储器存在故障.     

Optimization of test resources for 3D SoC based on game theory

The ever-increasing complexity of on-chip interconnection poses great challenges for the architecture of conventional system-on-chip (SoC) in semiconductor industry. The rapid development of process technology enables the creation of stacked 3-dimensional (3D) SoC by means of through-silicon-via (TSV). Stacked 3D SoC testing consists of two major issues, test architecture optimization and test scheduling. This paper proposed game theory based optimization of test scheduling and test architecture to achieve win-win result as well as individual rationality for each player in a game. Game theory helps to achieve equilibrium between two correlated sides to find an optimal solution. Experimental results on handcrafted 3D SoCs built from ITC’2 benchmarks demonstrate that the proposed approach achieves comparable or better test times at negligible computing time.