Low-pressure chemical-vapor-deposited silicon-rich oxides fornonvolatile memory applications

The electrical and reliability characteristics of ultrathin nonstoichiometric silicon oxide (SiO_x, x<2) films deposited by the low-pressure chemical vapor deposition (LPCVD) technique using silane and nitrous oxide were studied. It has been found that these oxides exhibit enhanced current conduction at low electric field for both voltage polarities due to reduced conduction barrier height and a conduction mechanism that involves direct tunneling between dispersed silicon crystallites in the oxide. The current characteristics are controlled by adjusting the SiH₄/N₂O gas ratio. These nonstoichiometric films exhibit lower charge trapping, have an extremely large charge to breakdown, and there is negligible interface state generation in comparison to ultrathin thermal oxides. The results indicate that these highly reliable dielectrics can be promising candidates for nonvolatile memory applications     

Optimized trench MOSFET technologies for power devices

Low-voltage silicon trench power MOSFETs with forward conductivities approaching the silicon limit are reported. Vertical trench power MOSFETs with the measured performances of V_DB =55 V (R_sp=0.2 mΩ-cm², k _D=5.7 Ω-pF) and V_DB=35 V (R_sp=0.15 mΩ-cm², k_D =4.3 Ω-PF) were developed where V_DB is the drain-source avalanche breakdown voltage, R_sp is the specific on-state resistance, and k_D=R _spC_sp is the input device technology factor where C_sp is the specific MOS gate input capacitance. The optimum device performance resulted from an advanced trench processing technology that included (1) an improved RIE process to define scaled vertical silicon trenches, (2) silicon trench sidewall cleaning to reduce the surface damage, and (3) a novel polysilicon gate planarization technique using a sequential oxidation/oxide etchback, process. The measured performances are shown to be in excellent agreement with the two-dimensional device simulations and the calculated results obtained from an analytical model     

Effect of arsenic implantation on electrical characteristics ofLPCVD WSi2/n-Si Schottky contacts

Electrical characteristics of As-implanted low-pressure chemical vapor deposition (LPCVD) WSi₂/n-Si Schottky barriers are reported. It is shown that As implantation results in a significant Schottky-barrier lowering and an increase in the diode ideality factor n. Silicide annealing prior to As implantation is more effective in reducing Schottky-barrier height. Nearly ohmic characteristics were obtained for As-implanted LPCVD WSi₂ Schottky barriers. Arsenic implanted into high-temperature annealed silicide films was more effective in reducing the effective Schottky-barrier height. Detailed SIMS analysis indicated higher As concentration at the silicide/silicon interface when implanted into high-temperature-annealed silicide films     

Reduction of oxide charge and interface-trap density in MOScapacitors with ITO gates

The electrical properties of MOS capacitors with an indium tin oxide (ITO) gate are studied in terms of the number density of the fixed oxide charge and of the interface traps N_f and N _it, respectively. Both depend on the deposition conditions of ITO and the subsequent annealing procedures. The fixed oxide charge and the interface-trap density are minimized by depositing at a substrate temperature of 240°C at low power conditions and in an oxygen-rich ambient. Under these conditions, as-deposited ITO films are electrically conductive. The most effective annealing procedure consists of a two-step anneal: a 45-s rapid thermal anneal at 950°C in N₂, followed by a 30 min anneal in N₂/20% H₂ at 450°C. Typical values obtained for N_it and N_f are 4.2×10¹⁰ cm^-2 and 2.8×10¹⁰ cm^-2, respectively. These values are further reduced to 1.9×10¹⁰ cm^-2 and ≲5×10⁹ cm^-2, respectively, by depositing approximately 25 nm polycrystalline silicon on the gate insulation prior to the deposition of ITO     

An improved method to correlate measured circuit speed withsimulation [CMOS gate arrays]

The relationship between the measured propagation delay of elementary circuits and the values obtained by circuit SPICE modeling was studied. Systematic and random variations of L_eff of the actual circuit from the modeled values L_eff, which were extracted from separate test devices, were identified as a major source of error. The error was significantly reduced by an improved method to obtain the values of L_eff within the logic circuits, thus permitting accurate circuit performance modeling and the required technology optimization     

Ultradry annealing after polysilicon electrode formation forimproving the TDDB lifetime of ultrathin silicon oxide films in MOSdiodes

Effects of ultradry annealing on time-dependent dielectric breakdown (TDDB) lifetime (T_TDDB) were investigated for Si MOS diodes with 5-nm-thick silicon oxide and P-doped polysilicon gate electrode films. This annealing was performed at 800°C in ultradry N₂ of less than 1-ppm moisture concentration after the electrode formation. Under an accumulation-bias stress condition, T_TDDB for the ultradry-annealed n-type Si diodes was larger than that for the conventionally annealed ones, while such T _TDDB enhancement was not confirmed in the p-type ones. Since positive charges induced near anode-side oxide interfaces are closely related to T_TDDB, the T_TDDB enhancement for the ultradry-annealed n-type Si diodes probably reflects a qualitative improvement of the anode-side, i.e., gate-electrode-oxide, interfaces by ultradry annealing     

Power-supply voltage impact on circuit performance for half andlower submicrometer CMOS LSI

Based on theoretical understanding, the concept that the lower power supply voltage limit can be simply expressed by 1.1E_cL_eff, where E_c is the critical electric field necessary to cause carrier velocity saturation and L_eff is the effective channel length, is introduced. Experimental results confirmed that 1.1E_cL_eff predicts a good guideline for power-supply voltage for CMOS devices over a wide range of gate oxide thickness (7-45 nm) and design rule (0.3-2.0 μm). On the basis of theoretical models and experimental results, trends for power-supply voltage with MOS device scaling are demonstrated. It is shown that 1.1E_cL_eff can be regarded as the lower power-supply voltage limit in order to maintain the improvement in delay time for below 0.6-μm channel length at reduced power supply. The transconductance behavior for a MOSFET under high electric fields was investigated in order to explain the physical meaning of 1.1E_cL_eff     

Electrical properties of silicon dioxide films fabricated at 700°C. I: Pyroltsis of tetraethoxysilane

We have studied the effects of different deposition and annealing ambients on silicon dioxide films produced via the pyrolytic decomposition of tetraethoxysilane at 700° C. The oxide and interface charge characteristics of capacitors incorporating these oxides were measured. The results of these studies were as follows. (1) Films deposited in nitrogen exhibited very poor electrical properties. This was due to the poor quality of both the LPCVD oxide bulk (manifest as a hysteretic instability exceeding one Volt in 20 nm films) and the LPCVD oxide-silicon interface (interface trap charge and fixed charge exceeding 10¹² cm⁻²). These characteristics were not improved by post-deposition annealing in nitrogen at 700° C. (2) As much as an order-of-magnitude reduction in interface traps and/or bias-induced drifts was obtained by exposure of the silicon substrate to 700°C oxygen ambients before, during, or after pyrolysis. The maximum improvement also required both post-deposition and post-metallization annealing treatments in nitrogen.     

Electrical properties of silicon dioxide films fabricated at 700°C. II: Low pressure hydride deposition

We have investigated the effects of different annealing treatments on silicon dioxide films produced from the reaction of dichlorosilane and nitrous oxide at 700° C. The electrical quality of these LPCVD films was evaluated by measuring oxide charge and interface trap densities on metal oxide semiconductor (MOS) capacitors. These densities were measured before and after avalanche injection of electron currents into the oxide films. The results of these studies were as follows. (1) The LPCVD oxide films required a post deposition anneal at 1000° C to produce as-grown charge densities similar to those of a standarddry thermal oxide grown and annealed at 1000° C. (2) Post-injection charge densities of LPCVD films given a post deposition anneal at 1000°C were an order of magnitude greater than those of the standard dry thermal oxide. (3) Different annealing treatments produced a series of dominant electron trapping centers in the oxide bulk₁₇ with capture cross sections ranging from 10⁻¹⁴ cm² to 10⁻¹⁷ cm². (4) The electron traps in the LPCVD oxides films were similar to those previously observed in standardwet thermal oxides grown and annealed above 1000° C.     

A model for hot-electron-induced MOSFET linear-current degradationbased on mobility reduction due to interface-state generation

A simple model for the hot-electron degradation of MOSFET linear-current drive is developed on the basis of the reduction of the inversion-layer mobility due to the generation of interface states. The model can explain the observed dependence of the device hot-electron lifetime on the effective channel length and oxide thickness by taking into account both the relative nonscalability of the localized damage region and the dependence of the linear-current degradation on the effective vertical electric field E_eff. The model is verified for deep-submicrometer non-LDD n-channel MOSFETs with L_eff=0.2-1.5 μm and T_ox=3.6-21.0 nm. From the correlation between linear-current and charge-pumping degradation, the scattering coefficient α, which relates the number of generated interface states to the corresponding amount of inversion-layer mobility reduction, can be extracted and its dependence on E_eff determined. Using this linear-current degradation model, existing hot-electron lifetime prediction models are modified to account explicitly for the effects of L_eff and T _ox     

On the electrical conduction in the interpolysilicon dielectriclayers

To reduce the low-field electrical conductivity of interpolysilicon dielectrics used in electrically erasable programmable read-only (EEPROM) memories devices, the roughness of the poly-SiO₂ interface until now has been decreased in two ways: (1) by increasing the temperature of oxidation and doping of polysilicon combined with low-pressure chemical vapor deposition (LPCVD) of silicon (undoped or in-situ doped) in the amorphous phase, or (2) by the use of LPCVD high-temperature oxide (HTO) deposited over polycrystalline silicon. The advantages of both methods are combined, and electrical conduction results for an interpoly structure based on LPCVD smooth surface polysilicon and LPCVD HTO SiO₂ are presented. The data are interpreted in terms of the Fowler-Nordheim mechanism     

Multigigahertz CMOS dual-modulus prescaler IC

A low-power CMOS dual-modulus (divide-by-128/129) prescaler IC is described. The IC has been fabricated with symmetric CMOS technology that optimizes simultaneously the characteristics of both the p-channel and n-channel transistors for low-power-supply-voltage operation. Two different gate oxide thicknesses of 175 and 100 Å have been used. The best prescalar fabricated with 175-Å gate oxide functions at 2.06 GHz with 25-m W power consumption (L_eff=0.5 μm; V_dd=3.5 V). Preliminary results for prescalars fabricated with 100-Å gate oxide show that 4.2-GHz operation is possible (L_eff=0.4 μm; V _dd=3.5 V). Power-supply voltage as low as 1.7 V can be used for the prescalar to function at 1 GHz with a power consumption of only 4 mW     

Optimum codes of dimension 3 and 4 over GF(4)

n_q(k,d), the length of a q-ary optimum code for given k and d, for q=4 and k=3, 4 is discussed. The problem is completely solved for k=3, and the exact value of n₄(4,d) is determined for all but 52 values of d     

Defect electrical conduction in SIMOX buried oxides

It is pointed out that the buried oxide (BOX) layers in SIMOX structures exhibit localized defect conduction superimposed on the background (bulk) conduction. Type I defects show a pre-breakdown quasi-linear I-V characteristic with 10^-7<I<10^-3 A in the voltage range of 0.01-10 V. Type II defects exhibit a superlinear I-V behavior above 5 V and breakdown, usually occurs at 10-50 V. A large number of samples prepared in various manners has been studied with automatic test equipment by which the number of Type I defects has been determined from several hundreds of capacitors on a given wafer. For annealed samples the calculated defect density values range from 0.01 to 10 defects/cm², while for un-annealed samples the range is 40-120 defects/cm². Type I defects are very probably Si pipes in the BOX which result from particulate contamination during implantation. Statistical analysis revealed that the sample preparation technique has improved significantly in 1992. The situation regarding the Type II defects is more complicated as these defects appear to be closely related to some fundamental aspects of bulk conduction of the BOX layer in which electron traps play an important role     

MICROX-an all-silicon technology for monolithic microwaveintegrated circuits

An improved silicon-on-insulator (SOI) approach offers devices and circuits operating to 10 GHz by providing formerly unattainable capabilities in bulk silicon: reduced junction-to-substrate capacitances in FETs and bipolar transistors, inherent electrical isolation between devices, and low-loss microstrip lines. The concept, called MICROX (patent pending), is based on the SIMOX process, but uses very-high-resistivity (typically>10000 Ω-cm) silicon substrates, MICROX NMOS transistors of effective gate length 0.25 μm give a maximum frequency of operation, f_max, of 32 GHz and f_T of 23.6 GHz in large-periphery (4 μm×50 μm) devices with no correction for the parasitic effects of the pads. The measured minimum noise figure is 1.5 dB at 2 GHz with associated gain of 17.5 dB, an improvement over previously reported values for silicon FETs     

Studies on aluminium corrosion during and after HF vapour treatment

The behaviour of aluminium during anhydrous hydrofluoric acid (HF) vapour etching of silicon dioxide films deposited by different methods was studied. Silicon dioxide films were grown by plasma-enhanced chemical vapour deposition (PECVD), low-pressure chemical vapour deposition (LPCVD), and a thermally oxidizing method. The etch rate of different oxides varies a lot. Etching of PECVD oxide causes residues on the aluminium surface as LPCVD and thermal oxide do not. The origin of the residues and different preventative methods are proposed.     

Rapid isothermal processing of strained GeSi layers

A cold-wall rapid thermal processor was used to study the oxidation and annealing properties of Ge_xSi_1-x strained layers. The dry oxidation rate of Ge_xSi_1-x was found to be the same as that of Si, while the wet oxidation rate was found to be higher than that of Si, and the oxidation rate increases with the Ge concentration (up to 20% in this study). A high fixed oxide charge density (>5×10¹¹ /cm²) and interface trap level density (>10¹² /cm²-eV) at the oxide interface have been determined from capacitance-voltage measurements. Using techniques such as X-ray rocking curve analysis and I-V and C-V measurements of the p-n heterojunction it was found that the degradation of electronic properties of metastable Ge_xSi_1-x strained layers during rapid thermal annealing are related to the formation of structural defects at the heterointerfaces     

Measurements and modeling of the n-channel MOSFET inversion layermobility and device characteristics in the temperature range 60-300 K

Discussed is the use of the high-frequency split C-V method to measure accurately the effective mobility of the n-channel MOS transistor as a function of temperature, bulk charge Q _b, and inversion layer charge Q_i. The experimental data for Q_b and Q_i were verified by comparison with the results of numerical simulation. The results of the measurements were used to develop the mobility model, which is accurate in the 60-300 K temperature range. The proposed mobility model incorporates Coulombic, lattice, and surface roughness scattering modes and generalizes the previous model, which was limited to low-temperature operation of the MOSFET. The deviation from the universal (for different back biases) μ(E_eff) dependence, which becomes more pronounced at low temperatures and low E_eff, is included in the model and can be associated with the Coulomb scattering mechanism. The proposed model is verified by comparison of experimental data and simulated MOSFET I-V characteristics for different temperatures     

Combined effects of hot-carrier stressing and ionizing radiation inSiO2, NO, and ONO MOSFETs

N-channel MOSFETs with different gate dielectrics, such as silicon dioxide, silicon dioxide annealed in nitrous oxide (NO), and reoxidized nitrided oxide (ONO), were first hot-carrier (HC) stressed and then irradiated to a total dose of 1.5 Mrd. For equal substrate current stressing NO devices have the least degradation, whereas the threshold voltage (V_t) shift due to irradiation is maximum for these devices. For all three types of gate dielectrics the V _t shift due to irradiation of HC stressed devices was higher than that of the unstressed device. However, for ONO devices the V _t shift due to irradiation of the hot-electron stressed (stressing with V_d=V_g=6.5 V) device was less than that of the unstressed device     

The effects of source/drain resistance on deep submicrometer deviceperformance

As MOSFET channel lengths approach the deep-submicrometer regime, performance degradation due to parasitic source/drain resistance (R _sd) becomes an important factor to consider in device scaling. The effects of R_sd on the device performance of deep-submicrometer non-LDD (lightly doped drain) n-channel MOSFETs are examined. Reduction in the measured saturation drain current (R_sd=600 Ω-μm) relative to the ideal saturation current (R_sd=0.0 Ω-μm) is about 4% for L_eff=0.7 μm and T_ox =15.6 nm and 10% for L_eff=0.3 μm and T _ox=8.6 nm. Reduction of current in the linear regime and reduction of the simulated ring oscillator speed are both about three times higher. The effect of salicide technologies on device performance is discussed. Projections are made of the ultimate achievable performance