Modified register-exchange Viterbi decoder for low-power wireless communications

In this paper, a new implementation of the Viterbi decoder (VD), based on a modified register-exchange (RE) method, is proposed. Conceptually, the RE method is simpler and faster than the trace-back (TB) method. However, the disadvantage of the RE method is that every bit in the memory must be read and rewritten for each bit of information decoded. The proposed implementation adopts the "pointer" concept: a pointer is assigned to each register. Instead of copying the contents of one register to another, the pointer which points to the first register is altered to point to the second register. Power-dissipation, performance, memory size, and the speed of the survivor sequence management are analyzed for both the TB method, and the proposed RE method. The analysis indicates an average power reduction of 23% for the new VD, compared to the power dissipation of the VD described in the literature for the third generation of wireless applications. The bit-error rate is 10/sup -5/ with a signal-to-noise ratio of approximately 6.3 dB for a continuous, uncontrolled encoded sequence. Moreover, the memory requirements of the new implementation are reduced by half. All the read and write operations in the survivor sequence management are executed at the data rate frequency which increases the maximum frequency.     

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-μm CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems     

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

A novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T writes “1” through one NMOS and writes “0” using two NMOS pass transistors. The 7T has mean \((\mu )\) of 222.3 mV (74.1 % of supply voltage) for write trip point where 5T fails to write “1” at 300 mV. It gives mean \((\mu )\) of 276 mV (92 % of supply voltage) for read margin, while 5T fails due to read disturb at 300 mV. The hold static noise margin of 7T is maintained close to that of 5T. The read operation of 7T is 22.5 % faster than 5T and saves 10.8 % read power consumption. It saves 36.9 % read and 50 % write power consumption as compared to conventional 6T. The novel design of proposed 7T consumes least read power and achieves the lowest standard deviation as compared to other reported SRAM cells. The power consumption of 1 kb 7T SRAM array during read and write operations is 0.70\(\times \) and 0.65\(\times \), respectively, of 1 kb 6T array. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low-voltage supply without any write assist in UMC 90 nm technology node. Future applications of the proposed 7T cell can potentially be in low-voltage, ultra-low-voltage and medium-frequency operations like neural signal processor, sub-threshold processor, wide-operating-range IA-32 processor, FFT core and low-voltage cache operation.     

Memoryless Viterbi decoder

The problem of survival memory management of a Viterbi decoder (VD) was solved by introducing a novel pointer implementation for the register exchange method, where a pointer is assigned to each row of memory in the survivor memory unit (SMU). The content of the pointer which points to one row of memory is altered to point to another row of memory, instead of copying the contents of the first row to the second. In this paper, the one-pointer VD is proposed; if the initial state of the convolutional encoder is known, the entire SMU is reduced to only one row. Because the decoded data bits are generated in the required order, even this row of memory is dispensable. Thus, the one-pointer architecture, referred to as memoryless VD (MLVD), reduces the power consumption of a traditional traceback VD by approximately 50%, but has some performance degradation. A prototype of the MLVD with a one third convolutional code rate and a constraint length of nine is mapped into a Xilinx 2V6000 chip, operating at 25 MHz with a decoding throughput of more than 3 Mbps and a latency of two data bits.     

A new write/erase method to improve the read disturbcharacteristics based on the decay phenomena of stress leakage currentfor flash memories

This paper describes a new write/erase method for flash memory to improve the read disturb characteristics by means of drastically reducing the stress leakage current in the tunnel oxide. This new write/erase operation method is based on the newly discovered three decay characteristics of the stress leakage current. The features of the proposed write/erase method are as follows: 1) the polarity of the additional pulse after applying write/erase pulse is the same as that of the control gate voltage in the read operation; 2) the voltage of the additional pulse is higher than that of a control gate in a read operation, and lower than that of a control gate in a write operation; and 3) an additional pulse is applied to the control gate just after a completion of the write/erase operation. With the proposed write/erase method, the degradation of the read disturb life time after 10⁶ write/erase cycles can be drastically reduced by 50% in comparison with the conventional bipolarity write/erase method used for NAND type flash memory. Furthermore, the degradation can he drastically reduced by 90% in comparison with the conventional unipolarity write/erase method fur NOR-, AND-, and DINOR-type flash memory. This proposed write/erase operation method has superior potential for applications to 256 Mb flash memories and beyond     

Multi-valued static random access memory (SRAM) cell with single-electron and MOSFET hybrid circuit

A new multi-valued static random access memory (MVSRAM) cell with a hybrid circuit consisting of a single-electron (SE) and MOSFETs is proposed. The previously reported MVSRAM with an SE-MOSFET hybrid circuit needs two data lines, one bit line for write operations and one sense line for read operations, to improve the speed of the read-out operation, but the proposed cell has only one data line for read/write operations, resulting in a memory area that is much smaller than that of the previous cell, without any reduction of read-out speed.     

Design of a power-reduction Viterbi decoder for WLAN applications

In this paper, a 64-state four-bit soft-decision Viterbi decoder with power saving mechanism for high speed wireless local area network applications is presented. Based on path merging and prediction techniques, a survivor memory unit with hierarchical memory design is proposed to reduce memory access operations. It is found that more than 70% memory access can be reduced by taking advantage of locality. Moreover, a low complexity compare-select-add unit is also presented, leading to save 15% area and 14.3% power dissipation as compared to conventional add-compare-select design. A test chip has been designed and implemented in 0.18-/spl mu/m standard CMOS process. The test results show that 30/spl sim/40% power dissipation can be reduced, and the power efficiency reaches 0.75 mW per Mb/s at 6 Mb/s and 1.26 mW per Mb/s at 54 Mb/s as specified in IEEE 802.11a.     

Low standby leakage 12T SRAM cell characterisation

In this work, a low power and variability-aware static random access memory (SRAM) architecture based on a twelve-transistor (12T) cell is proposed. This cell obtains low static power dissipation due to a parallel global latch (G-latch) and storage latch (S-latch), along with a global wordline (GWL), which offer a high cell ratio and pull-up ratio for reliable read and write operations and a low cell ratio and pull-up ratio during idle mode to reduce the standby power dissipation. In the idle state, only the S-latch stores bits, while the G-latch is isolated from the S-latch and the GWL is deactivated. The leakage power consumption of the proposed SRAM cell is thereby reduced by 38.7% compared to that of the conventional six-transistor (6T) SRAM cell. This paper evaluates the impact of the chip supply voltage and surrounding temperature variations on the standby leakage power and observes considerable improvement in the power dissipation. The read/write access delay, read static noise margin (SNM) and write SNM were evaluated, and the results were compared with those of the standard 6T SRAM cell. The proposed cell, when compared with the existing cell using the Monte Carlo method, shows an appreciable improvement in the standby power dissipation and layout area.     

Efficient Loop Scheduling for Chip Multiprocessors with Non-Volatile Main Memory

Non-volatile memories (NVMs) show great potential in replacing DRAM as the main memory in many embedded systems because of their attractive characteristics such as low cost, high density, and low energy consumption. However, the problem of asymmetric read and write costs has to be addressed before the advantages of NVM can be fully exploited. That is, the cost of write operation is much more expensive than the cost of read operation on NVMs. The existing techniques for loop optimization cannot be used effectively with non-volatile main memory because this special feature is not considered. In this paper, we propose an efficient loop scheduling algorithm, the Rotation with Maximum Bipartite Matching (RMBM) algorithm, to address the problem of expensive write operations on non-volatile main memory for chip multiprocessors (CMPs). It achieves high parallelism for a loop and, at the same time, reduces the number of write operations on NVM. The experimental results show that the RMBM algorithm reduces the number of write activities on NVM by 34.5 % on average compared with the traditional rotation scheduling algorithm. The execution time is reduced by 20.5 %, and the energy consumption is also reduced by 15.03 % on average using the RMBM algorithm. In other words, the average lifetime of NVM can be extended by more than 2 times using the proposed technique.     

Kinetic inductance memory cell

A Josephson memory cell based on kinetic inductance is proposed and analyzed. The size of the cells can be as small as 1/100 that of conventional superconducting memory cells. However, the kinetic inductance memory cell cannot utilize magnetically coupled read and write circuitry. The authors propose a current injected read/write architecture     

A new architecture of photonic ATM switches

A photonic asynchronous transfer mode (ATM) switch architecture for ATM operation at throughputs greater than 1 Tbit/s is proposed. The switch uses vertical-to-surface transmission electrophotonic devices (VSTEPs) for the optical buffer memory, and an optical-header-driven self-routing circuit in contrast with conventional photonic ATM switches using electrically controlled optical matrix switches. The optical buffer memory using massively parallel optical interconnections is an effective solution to achieve ultra-high throughput in the buffer. In the optical-header-driven self-routing circuit, a time difference method for a priority control is proposed. For the optical buffer memory, the write and read operations to and from the VSTEP memory for 1.6 Gbit/s, 8-bit optical signal are confirmed. The optical self-routing operation and priority control operation by the time difference method in the 4×4 self-routing circuit were performed by 1.6-Gbit/s 256-bit data with a 10-ns optical header pulse     

Self-Organized Sub-bank SHE-MRAM-based LLC: An energy-efficient and variation-immune read and write architecture

In order to reduce static energy consumption, emerging Non-Volatile Memory (NVM) technologies such as Spin Transfer Torque Magnetic RAM (STT-MRAM), Spin-Hall Effect Magnetic RAM (SHE-MRAM), Phase Change Memory (PCM), and Resistive RAM (RRAM) are under intense research. Additionally, there is a demand for more reliable circuits as the technology scales due to increased error rates caused by the increased impact of Process Variation (PV). In order to combat PV-induced reliability problems, a novel approach is proposed herein that improves the reliability of read and write operations in emerging NVMs. In the proposed design, which is called the Self-Organized Sub-bank (SOS) approach, two Sense Amplifiers (SAs) have been adopted, one with improved reliability and one with improved energy efficiency profiles, in order to increase the performance of the read operation. In particular, based on the result of a Power-On Self-Test (POST), which detects PV-impact on sub-banks, SOS chooses between a reliable and an energy-efficient SA and assigns a preferred SA to each sub-bank. Furthermore, in order to increase the performance of the write operation, SHE-MRAM is replaced with STT-MRAM to provide better write energy profile. Additionally, SOS design is once implemented with a reliable write scheme and once with an energy-efficient write scheme and results are compared and analyzed. Based on the preliminary observation in our case study, 21.5% of read operations are extremely vulnerable to PV impacts. Our results indicate that the proposed SOS approach reduces the vulnerability of the read operation by 40% on average, hence reducing the fault propagation. In particular, the SOS alleviates Vulnerable False Data Sensing (VFDS) by 82% on average, while enhancing True Data Sensing (TDS) from 72.5% to 95% across all workloads studied herein compared to LLC with conventional STT-MRAM. Additionally, SOS using the reliable write circuit provides 161% improved Energy Delay Product (EDP) on average compared to SOS with conventional STT-MRAM, while providing less than 8% write current variation. On the other hand, SOS using energy-efficient write circuit offers 39% improved EDP on average compared to the SOS using reliable write circuit and 62% EDP improvement over conventional STT-MRAM.     

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.     

A Composite Circuit Model for NDR Devices in Random Access Memory Cells

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster read and write operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, a "composite" circuit model is presented that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the read/write performance metrics. Finally, comparisons of composite models are presented     

Cell-plate-line/bit-line complementary sensing (CBCS) architecturefor ultra low-power DRAMs

In the realization of gigabit scale DRAMs, one of the most serious problems is how to reduce the array power consumption without degradation of the operating margin and other characteristics. This paper proposes a new array architecture called cell-plate-line/bit-line complementary sensing (CBCS) architecture which realizes drastic array power reduction for both read/write operations and refresh operations, and develops a large readout voltage difference on the bit-line and cell-plate-line. For read/write operations, the array power reduces to only 0.2%, and for refresh operations becomes 36%, This architecture requires no unique process technology and no additional chip area. Using a test device with a 64-Mb DRAM process, the basic operation has been successfully demonstrated. This new memory core design realizes a high-density DRAM suitable for the 1-Gb level and beyond with power consumption significantly reduced     

Area-efficient VLSI architecture for the traceback Viterbi decodersupporting punctured codes

The authors present a novel architecture designed to reduce the storage for decision vectors at the traceback block in the Viterbi decoder. By decreasing the rate of decision vector generation, the data storage requirement has been reduced by 29.9% in the proposed architecture compared to conventional traceback Viterbi decoders. The overall area has been reduced by ~25% when implemented in VLSI     

Variation resilient subthreshold SRAM cell design technique

This article presents a circuit technique for designing a variability resilient subthreshold static random access memory (SRAM) cell. The architecture of the proposed cell is similar to the conventional 10T SRAM cell with the exception that dynamic threshold MOS is used for the read/write access FETs and cell content body bias scheme is used for bitline droppers (FETs used to drop bitlines). Moreover, the proposed bitcell utilises single differential port unlike conventional 10T bitcell which utilises dual differential ports. The proposed design offers 2.1× improvement in T _RA (read access time) and 3.2× improvement in T _WA (write access time) compared to CON10T at iso-device-area and 200?mV. It exhibits three roots in its read voltage transfer characteristic (VTC) even at 150?mV showing its ability to function as a bistable circuit. The combination of write and read VTCs for write static noise margin of the proposed design also shows single root signifying its write-ability even at 150?mV. It proves its robustness against process variations by featuring narrower spread in T _RA distribution (by 1.3×) and in T _WA distribution (by 1.2×) at 200?mV.     

A low power high speed MTJ based non-volatile SRAM cell for energy harvesting based IoT applications

Powering billions of devices is one of the most challenging barrier in achieving the future vision of IoT. Most of the sensor nodes for IoT based systems depend on battery as their power source and therefore fail to meet the design goals of lifetime power supply, cost, reliable sensing and transmission. Energy harvesting has the potential to supplant batteries and thus prevents frequent battery replacement. However, energy autonomous systems suffer from sudden power variations due to change in external natural sources and results in loss of data. The memory system is a main component which can improve or decrease performance dramatically. The latest versions of many computing system use chip multiprocessor (CMP) with on-chip cache memory organized as array of SRAM cell. In this paper, we outline the challenges involved with the efficient power supply causing power outage in energy autonomous/self-powered systems. Also, various techniques both at circuit level and system level are discussed which ensures reliable operation of IoT device during power failure. We review the emerging non-volatile memories and explore the possibility of integrating STT-MTJ as prospective candidate for low power solution to energy harvesting based IoT applications. An ultra-low power hybrid NV-SRAM cell is designed by integrating MTJ in the conventional 6T SRAM cell. The proposed LP8T2MTJ NV-SRAM cell is then analyzed using multiple key performance parameters including read/write energies, backup/restore energies, access times and noise margins. The proposed LP8T2MTJ cell is compared to conventional 6T SRAM counterpart indicating similar read and write performance. Also, comparison with the existing MTJ based NV-SRAM cells show 51–78% reduction in backup energy and 42–70% reduction in restore energy.     

Comprehensive study on a novel bidirectional tunnelingprogram/erase NOR-type (BiNOR) 3-D flash memory cell

In this paper a recently proposed bidirectional tunneling program/erase (P/E) NOR-type (BiNOR) flash memory is extensively investigated. With the designated localized p-well structure, uniform Fowler-Nordheim (FN) tunneling is first fulfilled for both program and erase operations in NOR-type array architecture to facilitate low power applications. The BiNOR flash memory guarantees excellent tunnel oxide reliability and is provided with fast random access capability. Furthermore, a three-dimensional (3D) current path in addition to the conventional two-dimensional (2D) conduction is proven to improve the read performance. The BiNOR flash memory is thus promising for low-power, high-speed, and high-reliability nonvolatile memory applications     

A ferroelectric DRAM cell for high-density NVRAMs

The operation of a ferroelectric DRAM (dynamic random access memory) cell for nonvolatile RAM (NVRAM) applications is described. Because polarization reversal only occurs during nonvolatile store/recall operations and not during read/write operations, ferroelectric fatigue is not a serious endurance problem. For a 3-V power supply, the worst-case effective silicon dioxide thickness of the unoptimized lead zirconate titanate film studied is less than 17 Å. The resistivity and endurance properties of ferroelectric films can be optimized by modifying the composition of the film. This cell can be the basis of a very-high-density NVRAM with practically no read/write cycle limit and at least 10¹⁰ nonvolatile store/recall cycles