Transistor characteristics with Ta2O5 gatedielectric

As the gate oxide thickness decreases below 2 nm, the gate leakage current increases dramatically due to direct tunneling current. This large gate leakage current will be an obstacle to reducing gate oxide thickness for the high speed operation of future devices. A MOS transistor with Ta₂O₅ gate dielectric is fabricated and characterized as a possible replacement for MOS transistors with ultra-thin gate silicon dioxide. Mobility, I_d-V_d, I_d-V_g, gate leakage current, and capacitance-voltage (C-V) characteristics of Ta₂O₅ transistors are evaluated and compared with SiO₂ transistors. The gate leakage current is three to five orders smaller for Ta₂O₅ transistors than SiO₂ transistors     

Promising storage capacitor structures with thin Ta2O5 film for low-power high-density DRAMs

To ensure the required capacitance for low-power DRAMs (dynamic RAMs) beyond 4 Mb, three kinds of capacitor structures are proposed: (a) poly-Si/SiO₂/Ta₂O₅/SiO₂ /poly-Si or poly-Si/Si₃N₄/Ta₂O ₅/SiO₂/poly-Si (SIS), (b) W/Ta₂O₅ /SiO₂/poly-Si (MIS), and (c) W/Ta₂O₅ W (MIM). The investigation of time-dependent dielectric breakdown and leakage current characteristics indicates that capacitor dielectrics that have equivalent SiO₂ thicknesses of 5, 4, and 3 nm can be applied to 3.3-V operated 16-Mb DRAMs having stacked capacitor cells (STCs) by using SIS, MIS, and MIM structures, respectively, and that 3 and 1.5 nm can be applied to 1.5-V operated 64-Mb DRAMs having STCs by using MIS and MIM structures, respectively. This can be accomplished while maintaining a low enough leakage current for favorable refresh characteristics. In addition, all these capacitors show good heat endurance at 950°C for 30 min. Therefore, these capacitors allow the fabrication of low-power high-density DRAMs beyond 4 Mb using conventional fabrication processes at temperatures up to 950°C. Use of the SIS structure confirms the compatability of the fabrication process of a storage capacitor using Ta₂O₅ film and the conventional DRAM fabrication processes by successful application to the fabrication process of an experimental memory array with 1.5-μm×3.6-μm stacked-capacitor DRAM cells     

Two-step annealing technique for leakage current reduction inchemical-vapor-deposited Ta2O5 film

A capacitor technology developed to obtain extremely thin Ta₂ O₅ dielectric film with an effective SiO₂ film thickness down to 3 nm (equivalent to 11 fF/μm²) for a 1.5-V, low-power, high-density, 64-Mb DRAM is discussed. The Ta₂ O₅ has low leakage current, low defect density, and excellent step coverage. The key process is two-step annealing after the deposition of the film by thermal chemical vapor deposition (CVD). The first step involves ozone (O₃) annealing with ultraviolet light irradiation, which reduces the leakage current. The second step is dry oxygen (O₂) annealing, which decreases the defect density. A more significant reduction in the leakage current is attained by the combination of the two annealing steps     

Thermally robust Ta2O5 capacitor for the256-Mbit DRAM

The thermal degradation of the Ta₂ O₅ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta₂O₅ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850°C. The Ta₂O₅ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained     

Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics     

Reduction of current leakage in chemical-vapor deposited Ta2O5 thin-films by oxygen-radical annealing [DRAMdielectric]

The electrical properties of CVD-Ta₂O₅ thin-films are improved by post-deposition oxygen-radical annealing. Since this annealing is carried out at very low pressure (10^-6 torr), the growth of SiO₂ in Ta₂O ₅/Si interface is small, and the residual carbon in the film is reduced. The damage to the Ta₂O₅ film caused by oxygen ion bombardment is negligible, because few charged particles reach the film. A critical voltage V_crit of 1.45 V for the leakage current less than 10^-8 A/cm² was realized by these Ta₂O₅ films with the effective thickness t_eff of 2.59 nm. The V_crit value for oxygen-radical annealing is higher than that for oxygen-plasma annealing     

The observation of negative transconductance effect caused byreal-space-transfer of electrons in metal oxide semiconductor fieldeffect transistors fabricated with Ta2O5 gatedielectric

N-channel metal oxide semiconductor field effect transistors (MOSFETs) with Ta₂O₅ gate dielectric were fabricated. An intrinsic Ta₂O₅/silicon barrier height of 0.51 eV was extracted from the gate current. The effective Ta ₂O₅/silicon barrier height including image force barrier lowering is about 0.37 eV with drain to source voltage V_DS ranging from 1.5 V to 4.0 V. Due to the low barrier height, negative transconductance effect was observed in the linear region. The decrease of drain current is due to the real space transfer of electrons from the drain terminal to the gate electrode     

Ta2O5/silicon barrier height measured fromMOSFETs fabricated with Ta2O5 gate dielectric

N-channel metal oxide semiconductor field effect transistors with Ta₂O₅ gate dielectric were fabricated. The Ta₂O₅/silicon barrier height was calculated using both the lucky electron model and the thermionic emission model. Based on the lucky electron model, a barrier height of 0.77 eV was extracted from the slope of the ln(I_g/I_d) versus ln(I_sub/I_d) plot using an impact ionization energy of 1.3 eV. Due to the low barrier height, the application of Ta₂ O₅ gate dielectric transistors is limited to low supply voltage preferably less than 2.0 V     

Leakage current reduction in chemical-vapor-depositedTa2O5 films by rapid thermal annealing in N2O

This study aims to improve the electrical characteristics and reliability of low-pressure chemical vapor deposited (LPCVD) Ta₂ O₅, films by developing a new post-deposition single-step annealing technique. Experimental results indicate that excited oxygen atoms generated by N₂O decomposition can effectively repair the oxygen vacancies in the as-deposited CVD Ta₂ O₅ film, thereby resulting in a remarkable reduction of the film's leakage current. Two other post-deposition annealing conditions are compared: rapid thermal O₂ annealing and furnace dry-O₂ annealing. The comparison reveals that RTN₂O annealing has the lowest leakage current, superior thermal stability of electrical characteristics and the best time-dependent dielectric breakdown (TDDB) reliability     

Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Oxidized Ta2O5/Si3N4dielectric films on poly-crystalline Si for dRAMs

A dielectric film technology characterized by a novel multilayer structure formed by oxidation of Ta₂O₅/Si₃ N₄ films on polysilicon has been developed to realize high-density dRAMs. The dry oxidation of the Ta₂O₅/Si₃N₄ layers was performed at temperatures higher than 900°C. This film has a capacitance per unit area from 5.5 to 6.0 fF/ μm², which is equivalent to that of a 6.0- to 6.5-nm-thick SiO₂. The leakage current at an effective electric field of 5 MV/cm is less than 10^-9 A/cm². Under such an electric field, the extrapolated time to failure for 50% cumulative failure can be as high as 1000 years     

Roughness of ZnS:Pr,Ce/Ta2O5 interface andits effects on electrical performance of alternating current thin-filmelectroluminescent devices

Roughness effects of neighboring dielectrics on electrical characteristics of thin-film electroluminescent devices were investigated in order to improve the understanding of physics for the devices. Atomic force microscopy analysis reveal that thicker bottom layer of Ta₂O₅ shows rougher surface resulting in the rougher surface of ZnS:Pr,Ce layer. It can be easily seen that the dc leakage current increases rapidly with increase of surface roughness. Furthermore, it is notable that the initiation field of Poole-Frenkel current conduction is lowered by increasing surface roughness of Ta₂O₅ thin film. Internal charge-phosphor field (Q _int-F_p) analysis and capacitance-ac voltage (C-V) analysis for ITO-Ta₂O₅-ZnS:Pr,Ce-Al and ITO-Ta₂O₅-ZnS:Pr,Ce-Ta₂O₅-Al show that the steady state phosphor field is smaller and C-V curve in transition region is less steep with increase of root-mean-square roughness between lower dielectric and phosphor layer in the alternating current thin-film electroluminescent (ACTFEL) devices. Therefore, we conclude that interface roughness is one of the physical factors to change the electrical performance of ACTFEL device     

Reduction of leakage current in chemical-vapor-deposited Ta2O5 thin films by furnace N2O annealing

In this brief, we present a post-deposition annealing technique that employs furnace annealing in N₂O (FN₂O) to reduce the leakage current of chemical-vapor-deposited tantalum penta-oxide (CVD Ta₂O₅) thin films. Compared with furnace annealing in O₂ (FO) and rapid thermal annealing in N ₂O (N₂O), FN₂O annealing proved to have the lowest leakage current and the most reliable time-dependent dielectric breakdown (TDDB)     

Low-loss polyimide-Ta2O5-SiO2hybrid ARROW waveguides

A low-loss polyimide-Ta₂O₅-SiO₂ hybrid antiresonant reflecting optical waveguide (ARROW) is presented. The ARROW device was fabricated using both the organic and dielectric thin-film technologies. It consists of the fluorinated polyimide, tantalum pentoxide (Ta₂O₅), and silicon dioxide (SiO₂) hybrid layers deposited on a Si substrate. For transverse electric polarized light, the propagation loss of the waveguide as low as 0.4 dB/cm was obtained at 1.31 μm. The propagation loss for transverse magnetic polarized light is 1.5 dB/cm. An ARROW waveguide fabricated using the polyimide-Ta₂O₅ -polyimide material system is also presented for comparison     

Development of Embedded Three-Dimensional 35-nF/mm2 MIM Capacitor and BiCMOS Circuits Characterization

This paper summarizes the electrical characterization of MIM capacitor realized in three dimensions. Manufacturing of the device is described, as well as an electrical comparison of three dielectrics, Si₃N₄, Al₂O₃, Ta₂O₅ and two deposition methods, metal organic chemical vapor deposition (MOCVD) and atomic layer deposition (ALD). Selecting Al₂O₃ deposited by ALD, high density of 35 nF/mm² is obtained with low leakage current. Statistical measurements put forward the industrial robustness of the device integrated in BiCMOS technology. Three circuits embedding this new device are characterized: a high-pass filter, a voltage-controlled oscillator (VCO), and a phase-locked loop (PLL). They demonstrate excellent performances with significant area and assembly costs savings.     

Low-loss proton-exchanged waveguide in MgO-doped LiNbO3fabricated with pyrophosphoric acid using Ta2O5protective mask

The authors describe low-loss proton-exchanged channel waveguides in MgO-doped LiNbO₃. The authors demonstrate the application of a Ta₂O₅ film for the protective mask material in proton-exchanging instead of a Ta film in order to reduce the propagation loss. A Ta₂O₅ sputtered film was applied as a protective mask with pyrophosphoric acid. The propagation loss of the waveguide, measured with laser diode light (λ=0.83 μm) was 0.5 dB/cm. It is shown that the use of a Ta₂O₅ mask reduces the propagation loss compared with the use of a Ta mask (1.5 dB/cm)     

MOS transistors with stacked SiO2-Ta2O5-SiO2 gate dielectrics for giga-scale integration ofCMOS technologies

Advances in lithography and thinner SiO₂ gate oxides have enabled the scaling of MOS technologies to sub-0.25-μm feature size. High dielectric constant materials, such as Ta₂O₅ , have been suggested as a substitute for SiO₂ as the gate material beyond t_ox≈25 Å. However, the Si-Ta ₂O₅ material system suffers from unacceptable levels of bulk fixed charge, high density of interface trap states, and low silicon interface carrier mobility. In this paper we present a solution to these issues through a novel synthesis of a thermally grown SiO₂(10 Å)-Ta₂O₅ (MOCVD-50 Å)-SiO₂ (LPCVD-5 Å) stacked dielectric. Transistors fabricated using this stacked gate dielectric exhibit excellent subthreshold behaviour, saturation characteristics, and drive currents     

Design optimization of stacked layer dielectrics for minimum gate leakage currents

An effective model to evaluate the leakage currents for different stacked gates deep submicron MOS transistors is presented. For a given equivalent oxide thickness of a stacked gate, the gate leakage current decreases with an increase of high-k dielectric thickness or a decrease of interlayer thickness. Turning points at high gate biases of the I–V curves are observed for Si₃N₄/SiO₂, Ta₂O₅/SiO₂, Ta₂O₅/SiO_2−yN_y, Ta₂O₅/Si₃N₄, and TiO₂/SiO₂ stacked gates except for Al₂O₃/SiO₂ structure. Design optimization for the stacked gate architecture to obtain the minimum gate leakage current is evaluated.     

Fabrication and characterization of Si-MOSFET's with PECVDamorphous Ta2O5 gate insulator

Silicon MOS transistors having amorphous Ta₂O₅ insulator gates have been fabricated. The Ta₂O₅ films were deposited using a low pressure (a few mtorr) plasma-enhanced CVD process in a microwave (2.45 GHz) excited electron cyclotron resonance reactor. The source gas was TaF₅. Electrical characteristics of p-channel Al gate transistors are presented     

Fabrication of Submicrometer High Refractive Index Tantalum Pentoxide Waveguides for Optical Propulsion of Microparticles

Design, fabrication, and optimization of tantalum pentoxide (Ta₂O₅ ) waveguides to obtain low-loss guidance at a wavelength of 1070 nm are reported. The high-refractive index contrast (Deltan ~ 0.65, compared to silicon oxide) of Ta₂O₅ allows strong confinement of light in waveguides of submicrometer thickness (200 nm), with enhanced intensity in the evanescent field. We have employed the strong evanescent field from the waveguide to propel micro-particles with higher velocity than previously reported. An optical propelling velocity of 50 mum/s was obtained for 8-mum polystyrene particles with guided power of only 20 mW.