Effects of dielectric losses on the performance of evaporated thin-film distributed RC notch filters

The effects of dielectric dissipation have been included in studies of distributed RC notch filter networks, and it is shown that these may have considerable influence on the magnitude of the optimum notch parameter /spl alpha//SUB 0,1/ and the location of the lowest order optimum notch frequency /spl omega//SUB 0,1/. Voltage transfer function relationships, incorporating a frequency-dependence dissipation factor B(/spl omega/), are given for uniform and exponentially tapered structures. The measured transfer responses of aluminium-silicon monoxide-nichrome evaporated thin-film notch structures were in good agreement with these values predicted. Uniformly distributed RC notch filters exhibited optimum notch attenuations of 71 dB, while exponentially tapered RC filters with taper D=+1 gave 62-dB optimum notch attenuation together with reduced rejection band width.     

An analysis of a super wide–band FM line discriminator

This paper presents a dynamic analysis of an extremely wide-band FM line discriminator consisting of a pair of transmission lines and coupling resistors. The relationship between the harmonic distortion of the output waveform of the discriminator and the permissible frequency deviation of the input signal is analyzed in detail by the method of Fourier transform. It is shown that the coupling resistor constant γ (see Fig. 1) should be set at unity from the viewpoint of the sensitivity of the discriminator and the constant input impedance of the discriminator over the frequency deviation of the input signal. Theoretically, an FM signal having 100 per cent frequency deviation could be detected by this discriminator with 2.67 per cent harmonic distortion while the input impedance of the discriminator remains constant (equal to characteristic impedance of the transmission line Z0) during the frequency deviation. Experimental results are presented to verify the theoretical results obtained. The characteristic curve of the discriminator is linear for 40 per cent frequency deviation from the carrier frequency 85.5 Mc, and its input impedance remains within ±14 per cent of the idea value Z0.     

Monolithic analog multiplier-divider

The design of a precision general-purpose monolithic analog multiplier-divider based on the principle of the variable transconductance of bipolar transistors is described. The device has two new aspects: first, an eight-transistor multiplier-divider core, and second, an improvement in the accuracy and high-frequency behavior of the input and output circuits having monolithic conversion resistors. The transfer function /spl nu//SUB w/=/spl nu//SUB x//spl nu//SUB y///spl nu//SUB z/ is only dependent on external voltages. An advantage of the multiplier-divider over a multiplier with a fixed internal voltage reference is that the external signal voltages can be accurately related to the relevant reference voltage. Moreover, the additional divider input enlarges the application field. The maximum signal voltages are /spl plusmn/10 V. The untrimmed inaccuracy is typically 2 percent. The nonlinearity is /spl plusmn/0.1 percent. The bandwidth is 6.5 MHz, and the slew rate is 50 V//spl mu/s.     

A fast overdrive-recovery amplifier

The design of an amplifier is presented which recovers from an overdrive within 0.005 percent in less than 30 ns after a /spl plusmn/10 V signal is applied to its input. The settling-time behavior of the amplifier is free from preshoot, overshoot, and ringing. Most importantly, the output of the amplifier remains unaffected by a capacitive load, if, for example, it is connected to an oscilloscope for visual display. The amplifier maintains a high gain linearity over its total dynamic range (/spl plusmn/0.1 percent), of which 80 percent is typically displayed on the screen of an oscilloscope. Such an amplifier, free from input and output interactions, is ideally suited for precise settling-time measurements of fast D/A converters and interface amplifier systems.     

High-power 1.3-/spl mu/m InGaAsP-InP amplifiers with tapered gain regions

Tapered structures fabricated in InGaAsP-InP 1.3-/spl mu/m quantum-well material have been evaluated as high-gain high-saturation-power amplifiers. The devices, which had a 1-mm-long ridge-waveguide input gain section followed by a 2-mm-long tapered section, demonstrated an unsaturated gain of 26 dB at 2.0 A and about 30 dB at 2.8 A. Saturated output power at 2.8 A was >750 mW. At 2.0-A drive current and /spl ap/10-mW input power, the relative intensity noise of the amplified signal was /spl les/-160 dB/Hz at frequencies /spl ges/2 GHz.     

A 250-MHz BiCMOS receiver channel with leading edge timing discriminator for a pulsed time-of-flight laser rangefinder

An integrated receiver channel of a pulsed time-of-flight (TOF) laser rangefinder for fast industrial measurement applications with the measurement accuracy of a few centimeters in the measurement range from /spl sim/1 m to /spl sim/30 m to noncooperative targets was developed. The receiver channel consists of a fully differential transimpedance amplifier channel, a peak detector, an rms meter and a timing discriminator. In this particular application there is no time to measure the received signal strength beforehand and it is not predictable from previous measurements, so a leading edge timing discriminator with a constant threshold voltage was used. The amplitude of the received pulse is measured with a peak detector and the amplitude information is used to compensate for the resulting walk error. The measured bandwidth of the receiver channel is 250 MHz, the maximum transimpedance 40k/spl Omega/ and the input-referred noise /spl sim/7pA//spl radic/Hz (C/sub photodiode/=2 pF). The timing detection accuracy of the receiver is better than /spl plusmn/35 mm in a single-shot measurement in a dynamic range of 1:4000 and a temperature range of 0/spl deg/C to +50/spl deg/C.     

A closer look at ring diode modulators

An ideal ring diode modulator will have an output containing only frequencies of the form (n/spl omega//SUB LO//spl plusmn//spl omega//SUB m/) where n is odd and /spl omega//SUB m/ is one of the signal input frequencies. It is shown that real ring behavior is critically dependent upon the diode's forward characteristic, in particular, the forward threshold voltage. This threshold is required to support signal potentials across the ring and together with the forward diode nonlinearity controls the switching response of the diode to applied potentials. An analysis of the ring is presented that takes these factors into account and predicts the experimentally observed product suppression maxima.     

High-speed operation of HTS SQUID-array interface circuits with a cryocooler

The authors evaluated the operation of high-temperature superconducting quantum interference device (SQUID)-array interface circuits (IFCs) with normal-metal control lines. Transimpedance amplification was obtained at an operating speed of 1 Gb/s using a cryocooler. The effect of the number of SQUIDs connected in series and the number of arrays connected in parallel on the level of output from the SQUID-array IFCs was examined by Josephson circuit simulation, and then the effect of statistical spreads of junction characteristics was evaluated by Monte Carlo simulation. It was found that the configuration of two parallel SQUID arrays with 64 SQUIDs gives the highest output when the junction characteristics in the arrays have a certain spread. The authors fabricated the IFCs by using the conventional interface-engineered junction process. The process reproducibility was 100 /spl mu/A /spl plusmn/25% for junction I/sub c/, and 3.02 pH /spl plusmn/5% and 2.57 pH /spl plusmn/17% for the sheet inductance of the upper and lower electrodes, respectively. The transimpedance at low frequencies reached 20 and 4 V/A for input levels of 20 and 100 /spl mu/A, respectively. Output voltages as high as 4.4 mV at 4.2 K and 2.3 mV at 40 K were obtained. Furthermore, an output voltage of 600 /spl mu/V was obtained for a 1-Gb/s 2/sup 15/-1 pseudo-random binary signal input at 40 K.     

A New Monolithic Voltage-Controlled Oscillator

A new monolithic voltage-controlled oscillator exploiting a previously reported monolithic variable capacitance cell is presented. With a 2.3 volt swing in control voltage, the oscillator generates a sinusoidal output signal at frequencies ranging from 55 MHz to 135 MHz. The total harmonic distortion is less than 1%, while frequency slew rate is greater than 16 MHz/ns.     

A harmonic injection-locked frequency divider in 0.18-/spl mu/m SiGe BiCMOS

A harmonic injection-locked frequency divider for high-speed applications is presented in this letter. In order to enhance the bandwidth of the high-order frequency division, a positive feedback is employed in the design of the subharmonic mixer loop. The proposed circuit is implemented in a 0.18-/spl mu/m SiGe BiCMOS process. With a singled-ended super-harmonic input injection of 0dBm, the frequency divider exhibits a locking range of 350MHz (from 59.77 to 60.12GHz) for the divide-by-four frequency division while maintaining an output power of -16.6/spl plusmn/ 0.5dBm within the entire frequency range. The frequency divider core consumes a dc power of 50mW from a 3.6-V supply voltage.     

A micropower fourth-order elliptical switched-capacitor low-pass filter

A micropower fourth-order elliptical switched-capacitor (SC) low-pass filter for biomedical applications has been designed and measured. The charge transfer error of an SC integrator using a transconductance amplifier is discussed. Also first-order noise and PSRR calculations are performed and compared with the results of simulations and measurements. The measurements show that by careful optimization of the gain bandwidth, slew rate, and gain of the amplifiers, high-performance low-power SC filters can be constructed. The cutoff frequency of the filter is 5 kHz, the ripple in the passband is 0.27 dB, and stopband rejection is 49 dB. The power consumption of the filter is 190 /spl mu/W with /spl plusmn/2.5-V power supplies. The dynamic range of the filter is 75 dB, and the total harmonic distortion over the whole passband range is below 0.25% for a 2-V/SUB pp/ input signal. The PSRR of the filter is above 40 dB at frequencies below 3 kHz.     

Ring-hybrid microwave voltage-variable attenuator using HFET transistors

In this paper, a voltage-variable microwave attenuator circuit is presented. The input signal first enters a rat-race power splitter where a 0/spl deg/ and a 180/spl deg/ pair of signals is generated. The 0/spl deg/ signal passes through a common-gate field-effect transistor (FET) that is fully turned on, with its gate voltage set to 0 V. The 180/spl deg/ signal enters another common-gate transistor biased in the triode region. By changing the gate voltage of the second FET, the amplitude of the 180/spl deg/ signal is varied. The in-phase and out-of-phase signals are summed at the output and variable attenuation is achieved. The concept was demonstrated experimentally from 3.0 to 3.4 GHz and a variable attenuation from 6 to 30 dB was achieved. The phase response is linear over the frequency band and exhibits a group delay of 0.71 ns. The input 1-dB compression point of the attenuator is 0 dBm and the second harmonic suppression is 18.5 dB at 0-dBm input power.     

A wide-range delay-locked loop with a fixed latency of one clock cycle

A delay-locked loop (DLL) with wide-range operation and fixed latency of one clock cycle is proposed. This DLL uses a phase selection circuit and a start-controlled circuit to enlarge the operating frequency range and eliminate harmonic locking problems. Theoretically, the operating frequency range of the DLL can be from 1/(N/spl times/T/sub Dmax/) to 1/(3T/sub Dmin/), where T/sub Dmin/ and T/sub Dmax/ are the minimum and maximum delay of a delay cell, respectively, and N is the number of delay cells used in the delay line. Fabricated in a 0.35 /spl mu/m single-poly triple-metal CMOS process, the measurement results show that the proposed DLL can operate from 6 to 130 MHz, and the total delay time between input and output of this DLL is just one clock cycle. From the entire operating frequency range, the maximum rms jitter does not exceed 25 ps. The DLL occupies an active area of 880 /spl mu/m/spl times/515 /spl mu/m and consumes a maximum power of 132 mW at 130 MHz.     

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated d.c. offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV r.m.s. input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55/spl deg/C.     

An analog GFSK modulator in 0.35-/spl mu/m CMOS

An analog Gaussian frequency shift keying (GFSK) modulator designed in 0.35-/spl mu/m CMOS consumes 600 /spl mu/A from a 3-V supply and realizes an analog implementation of the FM differential equation. The modulator operates at baseband and is intended for use in a direct-conversion Bluetooth transmitter. It achieves a frequency deviation of 160 kHz with better than /spl plusmn/3% accuracy. The modulator implements an amplitude control loop to achieve a well-defined output swing. The total output harmonic distortion is less than 1%.     

A high-frequency temperature-stable monolithic VCO

A new high-frequency monolithic voltage-controlled oscillator (VCO) is described that achieves /spl plusmn/60 ppm//spl deg/C temperature coefficient of frequency over 0-75/spl deg/C at center frequencies from DC to 20 MHz. The circuit also exhibits good linearity of voltage to frequency, and excellent triangle output waveform over the whole frequency range from low frequencies to 20 MHz. The circuit is fabricated using an eight mask IC process and has a die size of 65/spl times/50 mils/SUP 2/.     

A dual-differential analog shift register with a charge-splitting input and on-chip peripheral circuits

A very high degree of stability and the elimination of external support circuitry are requirements for many signal-processing applications of analog charge-coupled devices. A device that meets these requirements has been designed and fabricated. The device requires a single clock input signal and achieves a gain-temperature stability of /spl plusmn/0.015 dB over 0-50/spl deg/C and a gain-voltage stability of /spl plusmn/0.05 dB over a power-supply variation of /spl plusmn/10 percent. The NMOS device demonstrates the compatibility of digital, linear, and charge-coupled devices on a single chip.     

A synchronous phase-lock loop detector for integrated AM radio

A synchronous phase-lock loop AM detector has been realized on a single chip in a bipolar process with an f/SUB T/ of 400 MHz. The circuit accepts input signals at an IF frequency of 450-500 kHz with effective values between 20 and 100 mV. The phase-lock loop capture range is about 150 kHz. AM signals with over 80% modulation depth can be demodulated with less than 1% harmonic distortion in the audio output signal. The power dissipation of the chip is 120 mW at 8 V. The total chip size is 1900/spl times/1300 /spl mu/m/SUP 2/. Since the VCO and the 90/spl deg/ phase shift are completely realized on-chip, large signals at the IF frequency do not occur at the pins of the IC, and parasitic feedback of such signals to the IF amplifier input is minimized.     

Harmonic gain and noise in a frequency-doubling gyro-amplifier

Nonlinear gain in a 34-GHz three-stage frequency-doubling gyro-traveling wave tube (gyro-TWT) has been experimentally studied. The device consists of a thermionic electron gun, TE/sub 01//spl rarr/TE/sub 02/ fundamental gyro-TWT input section, second harmonic TE/sub 03/ intermediate buncher section, and a second harmonic TE/sub 02//spl rarr/TE/sub 04/ complex output circuit. Nonlinear bunching in the electron orbital phase generates harmonics of the input signal in the beam current, which excite the subsequent circuits at the second harmonic frequency. Since the gain is nonlinear, noise or applied sideband signals intermodulate with the carrier generating high-order products in the output. Therefore, it has been suggested that the noise figure of these devices may be unreasonably high. In this study, the complex harmonic transfer characteristics were experimentally measured and compared with calculations based on the assumption that the gyro-amplifier gain can be described, in the narrowband sense, as a classical frequency-doubling circuit. The results show that narrowband intermodulation gain is 6 dB higher than the carrier as predicted in the small signal limit, but as the device reaches saturation the nonlinear products become suppressed with respect to the carrier. Tests on the broadband gain characteristics show that output noise consists of second harmonic shot noise spontaneously excited in the output circuits along with the products of the intermodulation between external noise and the carrier. Good agreement between the experimental results and the calculations is demonstrated.     

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated dc offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV rms input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55°C.