Micromachined V-band CMOS bandpass filter with 2 dB insertion loss

A low-insertion-loss V-band CMOS bandpass filter is demonstrated. The proposed filter architecture has the following features: the low-frequency transmission-zero (vz1) and the high-frequency transmission-zero (vz2) can be tuned by the series-feedback capacitor Cs and the parallelfeedback capacitor Cp, respectively. To reduce the substrate loss, the CMOS process compatible backside inductively-coupled-plasma (ICP) deep trench technology is used to selectively remove the silicon underneath the filter. After the ICP etching, this filter achieved insertion loss (1/S21) lower than 3 dB over the frequency range 52.5?76.8 GHz. The minimum insertion loss was 2 dB at 63.5 GHz, the best results reported for a V-band CMOS bandpass filter in the literature.     

An ultralow-loss and broadband micromachined RF inductor for RFIC input-matching applications

In this brief, we demonstrate that ultralow-loss and broadband inductors can be obtained by using the CMOS process compatible backside inductively coupled-plasma (ICP) deep-trench technology to selectively remove the silicon underneath the inductors. The results show that a 378.5% increase in maximum Q-factor (Q/sub max/) (from 10.7 at 4.7 GHz to 51.2 at 14.9 GHz), a 22.1% increase in self-resonant frequency (f/sub SR/) (from 16.5 to 20.15 GHz), a 16.3% increase (from 0.86 to 0.9999) in maximum available power gain (G/sub Amax/) at 5 GHz, and a 0.654-dB reduction (from 0.654 dB to 4.08/spl times/10/sup -4/ dB) in minimum noise figure (NF/sub min/) at 5 GHz were achieved for a 2-nH inductor after the backside ICP dry etching. In addition, state-of-the-art ultralow-loss G/sub Amax//spl les/0.99 (i.e., NF/sub min//spl les/0.045 dB) for frequencies lower than 12.5 GHz was achieved for this 2-nH inductor after the backside inductively coupled-plasma dry etching. This means this on-chip inductor-on-air can be used to realize an ultralow-noise 3.1-10.6 GHz ultrawide-band RFIC. These results show that the CMOS process compatible backside ICP etching technique is very promising for system-on-a-chip applications.     

A highly linear CMOS low noise amplifier for K-band applications

This paper describes a highly linear low noise amplifier (LNA) for K-band applications in a 0.18 µm RF CMOS technology. The core of the circuit is a two-stage LNA consisting of a common-source and a cascode stage. By adopting an improved post-linearisation technique at the common-source transistor of the second stage, more than 5 dB improvement in IIP3 is achieved with a minor effect on noise figure and input matching. The circuit level analysis and simulation results are presented to demonstrate the effectiveness of the proposed technique.     

A high quality factor and low power loss micromachined RF bifilar transformer for UWB RFIC applications

In this letter, the authors demonstrate that high quality factor and low power loss transformers can be obtained by using the CMOS process-compatible backside inductively coupled plasma (ICP) deep-trench technology to selectively remove the silicon underneath the transformers. A 62.4% (from 8.99 to 14.6) and a 205.8% (from 8.6 to 26.3) increase in the Q-factor, a 10.3% (from 0.697 to 0.769) and a 30.2% (from 0.652 to 0.849) increase in the maximum available power gain (G/sub Amax/), and a 0.43- (from 1.57 to 1.14 dB) and a 1.15-dB (from 1.86 to 0.71 dB) reduction in the minimum noise figure (NF/sub min/) were achieved at 5.2 and 10 GHz, respectively, for a bifilar transformer with overall dimension of 240/spl times/240 /spl mu/m/sup 2/ after the backside ICP etching. The values of G/sub Amax/ of 0.769 and 0.849 are both state-of-the-art results among all reported on-chip bifilar transformers. These results indicate that the backside ICP deep-trench technology is very promising for high-performance radio frequency integrated circuit applications.     

0.13-μm CMOS Phase Shifters for X-, Ku-, and K-Band Phased Arrays

Two 4-bit active phase shifters integrated with all digital control circuitry in 0.13-mum RF CMOS technology are developed for X- and Ku-band (8-18 GHz) and K-band (18-26 GHz) phased arrays, respectively. The active digital phase shifters synthesize the required phase using a phase interpolation process by adding quadrature-phased input signals. The designs are based on a resonance-based quadrature all-pass filter for quadrature signaling with minimum loss and wide operation bandwidth. Both phase shifters can change phases with less than about 2 dB of RMS amplitude imbalance for all phase states through an associated DAC control. For the X- and Ku-band phase shifter, the RMS phase error is less than 10^o over the entire 5-18 GHz range. The average insertion loss ranges from to at 5-20 GHz. The input for all 4-bit phase states is typically at -5.4 plusmn1.3 GHz in the X- and Ku-band phase shifter. The K-band phase shifter exhibits 6.5-13 of RMS phase error at 15-26 GHz. The average insertion loss is from 4.6 to at 15-26 GHz. The input of the K-band phase shifter is at 24 GHz. For both phase shifters, the core size excluding all the pads and the output 50 Omega matching circuits, inserted for measurement purpose only, is very small, 0.33times0.43 mm² . The total current consumption is 5.8 mA in the X- and Ku-band phase shifter and 7.8 mA in the K-band phase shifter, from a 1.5 V supply voltage.     

SiC ICP背面通孔刻蚀研究

介绍了利用ICP设备,使用SF6基气体对4H-SiC衬底进行背面通孔刻蚀的技术。研究了金属刻蚀掩模、刻蚀气体中O2含量的变化、反应室压力、RF功率和ICP功率等各种条件对刻蚀结果产生的影响,重点对刻蚀气体中O2含量和反应室压力两个条件进行了优化。通过对刻蚀结果的分析,得出了适合当前实际工艺的优化条件,实现了厚度为100μm、直径为70μm的SiC衬底GaN HEMT和单片电路的背面通孔刻蚀,刻蚀速率达700nm/min,SiC和金属刻蚀选择比达到60∶1。通过对工艺条件的优化,刻蚀出倾角为75°～90°的通孔。     

Cl2/Ar/BCl3 ICP刻蚀对AlGaN的损伤研究

感应耦合等离子体(ICP)刻蚀在AlGaN基紫外探测器台面制作中起着重要作用,初步研究了Cl2/Ar/BCl3ICP刻蚀对AlGaN材料的损伤。运用X射线光电子能谱(XPS)对ICP刻蚀前后的n型Al0.45Ga0.55N表面进行了分析,并对刻蚀后AlGaN材料在N2气中快速热退火进行了研究。结果表明,在N2气中550°C退火3 min对材料的电学性能有明显的改善作用。     

A Low-Power Low-Noise Amplifier for K-Band Applications

This study presents a high performance K-band low noise amplifier. By utilizing transformer feedback at the input stage, an excellent noise figure (NF) of 4.3 dB is obtained at 22 GHz. With the current-reused technique between the two stages, the amplifier achieves a maximum power gain of 10.1 dB under a supply voltage of 1.8 V and a power consumption of only 7.2 mW. The proposed LNA has comparable NF and gain, while it can operate under the lowest power among the published works in 0.18 $mu{rm m}$ CMOS technology for K-band applications.      

A CMOS K-Band Quadrature Generator

This letter presents a K-band quadrature signal generator in a standard 0.13 mu m CMOS process. The quadrature generator operates from 18 to 21 GHz. A maximum output power of -3.7 dBm (per I or Q channel) is achieved, and the down converted signal suppression is >25 dB at the operating bandwidth. A measured sideband rejection ratio >30 dB is achieved from 19 to 21 GHz, with a peak of >40 dB at 19.5-20.5 GHz. The current consumption of the quadrature generator is 49-54 mA from a 2-2.5 V supply with an effective chip area of 0.51times 0.44 mm² . To the author's knowledge, this is the first demonstration of a K-band quadrature signal generator with high spectral purity and quadrature accuracy.     

Feasible approach for processes integration of CMOS transistor gate/side-wall spacer patterning fabrication

As the gate length is scaling down, the spacer design for CMOS transistor becomes increasingly critical manufacturing process. In recent CMOS technologies, side-wall spacers play an important role in the control of short channel effects by offsetting ion implantation profiles from the edge of the gate. The present approach to overcome these fabrication limitations. The spacer patterning technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical integrated lithography and etching processes. Generally relates to semiconductor manufacturing, and more particularly to nanotechnology fabrication feasibility for CMOS wafer process on gate spacer technology manufacture feasibility. A modified side-wall spacer patterning method was implemented for using conventional lithography and etching processing technology. Based on the systematical investigation of the effects of the various etch conditions on etching profile and their impacts on the sidewall transistor gate structure, a novel integrated process for well controlled side-wall spacer formation was developed for fabrication.     

深刻蚀高密度熔融石英光栅

深刻蚀高密度熔融石英光栅是一种新型高效的衍射光学元件,具有衍射效率高、成本低、抗损伤,能在高强度激光条件下工作等优点。给出了利用感应耦合等离子体(ICP)技术制作熔融石英深刻蚀光栅的详细过程,并在一定的优化条件下制作了一系列不同周期、开口比和深度的高质量深刻蚀石英光栅。实验得到的最大刻蚀深度为4μm,并且在600 l/mm的高密度条件下得到了刻蚀深度为1.9μm的高深宽比石英光栅。光栅侧壁陡直,表面平整,没有聚合物沉积。所制作的熔融石英光栅元件在高强激光环境、光谱仪、高效滤波器和波分复用系统等领域中有非常广泛的用途。     

SoI基微环谐振可调谐滤波器

采用电子束光刻和ICP刻蚀等工艺制作出绝缘体上Si(SoI)基纳米线波导微环谐振(MRR)滤波器,波导截面尺寸为300 nm×320 nm,微环半径为5 μm.测试结果表明,器件的自由频谱宽度(FSR)为16.8nm,1.55μm波长附近的消光比(ER)为18.1 dB.通过对MRR滤波器进行热光调制,在21.4～60...     

基于ICP的硅高深宽比沟槽刻蚀技术

介绍了电感耦合等离子体(ICP)刻蚀技术的基本概念。结合英国STS公司的STS multiplex ICP system刻蚀机,介绍了刻蚀机原理及刻蚀过程。对硅深槽刻蚀技术进行了分析,对其中Footing效应、Lag效应和侧壁光滑问题提出了优化方案,最后在实验的基础上得出了能够刻蚀出高质量硅深沟槽的刻蚀参数。     

Cl_2/Ar/BCl_3ICP刻蚀AlGaN的研究

感应耦合等离子体(ICP)刻蚀在AlGaN基紫外探测器台面制作中起着重要作用。在对比了ICP与RIE,ECR等干法刻蚀技术优缺点的基础上,采用Ni作为掩膜,Cl2/Ar/BCl3作为刻蚀气体,对金属有机化学气相淀积生长的n-Al0.45Ga0.55N进行了ICP刻蚀研究。刻蚀速率随着ICP直流偏压的增加而增加,刻蚀速率随着ICP功率的增加先增加较快后增加缓慢。最后结合刻蚀表面的扫描电镜(SEM)分析和俄歇电子能谱(AES)深度分析对刻蚀结果进行了讨论。分析表明,在满足刻蚀表面形貌的同时,较低的直流偏压下刻蚀速率较慢,但损伤较小,这对于制备高性能的紫外探测器是有利的。     

K-Band CMOS Sub-Harmonic Resistive Mixer With a Miniature Marchand Balun on Lossy Silicon Substrate

A K-band sub-harmonically pumped resistive mixer is demonstrated using standard 0.13 mum CMOS technology. A miniature Marchand Balun is integrated with the resistive mixer to generate equal amplitude and out-of-phase signals for mixer's local oscillation (LO) port directly on the lossy silicon substrate. The sub-harmonic resistive mixer with the integrated Marchand balun has conversion loss of 11-12 dB at f_IF = 100 MHz and P_LO = 7 dBm for RF frequencies from 18 to 26 GHz. The LO-RF and LO-IF isolations are approximately 30 and 33 dB, respectively.     

A 3.3 mW K-Band 0.18-μ m 1P6M CMOS Active Bandpass Filter Using Complementary Current-Reuse Pair

This letter presents a low-power active bandpass filter (BPF) at K-band fabricated by the standard 0.18 mum 1P6M CMOS technology. The proposed filter is evolved from the conventional half-wavelength resonator filter, using the complementary-conducting-strip transmission line (CCS TL) as the half-wavelength resonator. Furthermore, the complementary MOS cross-couple pair is proposed as a form of current-reuse scheme for achieving low-power consumption and high Q-factor simultaneously. The simulated results indicate that the Q-factor of the proposed half-wavelength resonator can be boosted from 9 to 513 at 25.65 GHz compared with the resonator enhanced by the nMOS cross-couple pair to Q-factor of merely 43 under the same power consumption. The proposed active BPF of order two occupies the chip area of 360 mum times 360 mum without contact pads. The measured results show that the center frequency of the active BPF is 22.70 GHz and a bandwidth of 1.68 GHz (7.39 %). The measured P_{1 dB} and noise figure at 22.70 GHz are -7.65 dBm and 14.05 dB, respectively. There is a 56.84 dB suppression between the fundamental tone and the second harmonic when the input power is -11.26 dBm. While showing 0 dB loss and some residual gain, the active BPF consumes 2.0 mA at 1.65 V supply voltage with maximum of 0.15 dB insertion loss and 9.96 dB return loss at pass band.     

ICP刻蚀在微加速度传感器制作中的应用

针对ICP刻蚀工艺进行了深入研究,探讨了气体流量、射频功率和工作室气压设定值等工艺参数对刻蚀效果的影响,最终在硅基底上获得了线宽为40μm时深刻蚀的最佳工艺参数,即采用BOSCH工艺,压力设定为6Pa,在刻蚀过程中通入流量为100cm3/min的SF6气体,持续11s,射频功率20W,源功率450W,保护过程中通入流量为75cm3/min的C4F8气体,持续10s,射频功率0W,源功率220W,得到了最佳刻蚀结果,并利用此工艺制作出了量程为±12g,灵敏度为79mV/g,精度高于±2%微机械加速度传感器。     

Low-noise amplifier in 0.12 /spl mu/m standard CMOS technology for K-band

A K-band CMOS low-noise amplifier with a noise figure of 4.26 dB and a peak gain of 18.86 dB is presented. The low-noise amplifier has a peak gain frequency of 20.3 GHz and an input referred 1 dB compression point of -16 dBm. These are believed to be the lowest noise figure and highest gain values reported to date at these frequencies in a standard CMOS technology.     

A low-phase-noise K-band CMOS VCO

A novel circuit topology for low-phase-noise voltage controlled oscillators (VCOs) is presented in this letter. By employing a PMOS cross-coupled pair with a capacitive feedback, superior circuit performance can be achieved especially at higher frequencies. Based on the proposed architecture, a prototype VCO implemented in a 0.18-/spl mu/m CMOS process is demonstrated for K-band applications. From the measurement results, the VCO exhibits a 510-MHz frequency tuning range at 20GHz. The output power and the phase noise at 1-MHz offset are -3dBm and -111dBc/Hz, respectively. The fabricated circuit consumes a dc power of 32mW from a 1.8-V supply voltage.     

适用于阵列波导光栅制作的厚SiO_2陡直刻蚀技术

采用ICP- 98型高密度等离子体刻蚀机进行了厚Si O2 陡直刻蚀技术的研究,利用双层掩膜技术解决了“微掩膜现象”问题,刻蚀获得12 .4 μm的陡直Si O2 光波导剖面,并将这一刻蚀技术用于阵列波导光栅的制作中.