一种新型结构的光电负阻器件

提出了一种新型结构的硅光电负阻器件--光电双耦合区晶体管(photoelectric dual coupled area transistor,PDUCAT),它是由一个P+N结光电二极管和位于两侧的两个纵向NPN管构成的.由于两个NPN管到光电二极管的距离不同,使得它们对光生空穴电流的争抢能力随外加电压的变化产生差异,同时两个NPN管电流放大系数相差较大,最终导致器件负阻现象的出现.文中对PDUCAT进行了工艺模拟和器件模拟,围绕着负阻的形成机理和影响器件性能的主要参数进行了讨论,初步建立了器件模型.     

硅光电负阻器件的光双稳态瞬态特性

在本文中,一方面对电路参数与硅光电负阻器件的光学双稳态开关时间的关系进行了研究,另一方面对器件在低、中、高三个不同输入光强区的光学双稳态响应的变化趋势进行了研究.硅光电负阻器件包括有各种类型,本文主要对"λ"型双极光电负阻晶体管(PLBT)以电阻和光电二极管作为负载的情况进行了讨论.     

光电双向负阻晶体管的数值模拟与实验研究

光电双向负阻晶体管(PBNRT)是一种新型S型光电负阻器件.本文对它的光电负阻特性进行了数值模拟和实验研究,给出了器件等效电路.PBNRT在光电混合工作模式下具有光控电流开关效应,可通过光照和控制电压两种控制方式改变器件的S型负阻特性.模拟和实验结果均表明:光照强度增大,维持电压基本保持不变,转折电压减小,负阻电压摆幅减小;而增大控制电压,维持电压和转折电压均增大,输出负阻特性曲线右移.上述特点使得PBNRT可望在光电开关、光控振荡和光电探测等方面有很好的应用前景.     

可作光子计数的雪崩光电二极管

对于光电倍增管不适用的高灵敏度弱光探测应用，存在一种固体替代器件，即雪崩光电二极管。这种器件在半导体内产生光电倍增，而光电倍增管在真空中产生电子倍增。雪崩光电二极管具有与半导体技术有关的微型化优点。由于这种器件能对单光子计数和探测很短时间间隔，它们已在光雷达、测距仪探测器和超灵敏光谱学方面找到日益增长的应用。另外，雪崩光电二极管在光纤通讯方面正与PIN光电二极管相竞争。雪崩光电二极管如何工作与任何光电二极管，样，雪崩光电二极管中由两类半导体组成的p-n结只允许电流在一个方向流动。光电二极管由一个掺有…     

Si光电负阻器件和Si-Ge异质结混合模式晶体管的模拟研究

“硅光负阻器件的研究”、“高频高速硅光负阻器件的研究”是国家自然科学基金和天津自然科学基金资助的项目,由天津大学电子信息工程学院微电子系新型器件小组承担研究工作。笔者围绕着该两项课题进行了硅光电负阻器件的基础研究工作,对两种硅光电负阻器件的机理进行了探讨。进行了二维器件模拟（简称器件模拟）,对影响器件性能的主要参数进行了模拟分析,并与实验进行了对比。建立了两种光电负阻器件的电路模型,并进行了实验验证。为光电负阻器件基础研究和应用研究打下了良好的基础。“SOI／SiGe/BiCMOS集成电路的研究”是国家自然科学基金重点项目,天津大学和清华大学共同承担了这项研究工作。笔者围绕着该项研究工作进行了SiGe/BiMOS的基础研究和设计工作,进行了器件模拟,对影响器件性能的主要参数进行模拟分析,模拟为器件设计提供了有意义的指导,完成版图设计和工艺设计。为SOI／SiGe/BiCMOS集成电路的研制奠定良好开端。具体研究的主要内容包括以下九个方面。     

DPLBT型高频硅光电负阻器件的研制

研制出特征频率fT≥220MHz,且具有较高光电灵敏度和最大峰值电流的光电负阻器件--达林顿光电λ型双极晶体管(DPLBT),并首先用发光二极管(LED)和光电负阻器件(DPLBT)封装成一种和常规光电耦合器不同的具有光电流开关、光控电流双稳态和光控正弦波振荡多种功能的新型光电耦合器(PCDPLBT).     

光电双基区晶体管(PDUBAT)物理模型探讨

本文通过分析器件内部电流传输探讨了光电双基区晶体管(PDUBAT)负阻特性产生机理,首次提出了PDUBAT负阻形成的原因是其输出管横向输出电流的反馈作用,这一看法得到了实验验证.     

双极晶体管发射极电阻的提取方法及应用研究

以双多晶自对准互补双极器件中NPN双极晶体管为例,阐述了发射极电阻提取的基本原理和数学方法。在大电流情况下,NPN管的基极电流偏离理想电流是发射极串联电阻效应引起的。该提取方法综合考虑了辐照过程中NPN管的电流增益退化特性,分析了总剂量辐照效应对NPN管的损伤机理和模式。该提取方法适用于多晶硅发射极器件,也适用于SiGe HBT器件。     

不同电极尺寸对光电二极管电流的影响

基于Sentaurus TCAD 软件对n-on-p型Hg1-xCdxTe红外探测器器件结构进行建模,并在不同电极尺寸条件下对器件的光电流进行仿真。通过仿真发现随着像元电极尺寸的减小,光电二极管反向电流也逐渐减小。针对这一现象从金属层对冶金结电势分布的影响和被吸收的光子数目Q两个角度进行了分析。金属层对半导体材料表面的电势分布具有调制作用,随着电极尺寸的减小,二极管的反向电流减小;随着像元电极尺寸的减小,被吸收的光子数目减小,导致光电二极管反向电流减小;以上两个方面都会引起光电二极管电流随着电极尺寸的减小而减小。     

三稳态共振隧穿器件的研制

在I-V特性曲线上具有双微分负阻的三稳态共振隧穿器件,室温下可以达到较高的电流峰谷比5.2∶1。器件采用两个隧穿二极管背靠背串联的结构,能更大程度提高集成度,可以在多值逻辑或其他有关降低电路复杂性方面获得较为广泛的应用。     

An exclusive-nor based on resonant interband tunneling FET's

We have proposed and demonstrated an XNOR device based on the negative differential resistance in a resonant interband tunneling diode and the current control capabilities of field effect transistors. DC and timing measurements have confirmed the operations of the device. Simulations and discussions will be presented     

激光制导四象限光电二极管的选择

四象限光电二极管是激光制导武器的核心部件,分析了其工作原理,并对光电二极管的结构,灵敏度方向性、噪声电流和频率响应时间选择作了分析.提出了噪声电流预存储和等带宽带外滤波两种消噪方法,可作为四象限光电二极管的选择和设计的基础.     

A novel dynamic memory cell with internal voltage gain

A 2T1D dynamic memory cell with two transistors (T) and a gated diode (D) is presented. A gated diode is a two terminal MOS device in which charge is stored when a voltage above the threshold voltage is applied between the gate and the source, and negligible charge is stored otherwise. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure, some hardware and test results are presented, followed by comparison to other memory cells and future directions.     

Determining the drain doping in DMOS transistors using the hump inthe leakage current

The hump in the leakage current of double-diffused metal-oxide-semiconductor (DMOS) transistors observed for low drain voltages is explained. This hump is due to surface generation current of the gate-controlled diode formed by the base-drain p-n junction. The drain bias of the DMOS transistor is shown to have the same effect on the charge at the drain surface as the body bias in the conventional MOSFET. The body effect is used to develop a new method for determining the drain doping in DMOS transistors. This method is nondestructive, and does not require special test structures. Instead, electrical measurements are performed on conventional DMOS transistors. The method is ideally suited for determining the doping in the drain region of interest. Specifically, in DMOS transistors in which a surface implant is used to reduce the on-resistance, the method provides the doping concentration in the implanted region. In DMOS transistors which do not have the surface implant, the method yields the doping concentration in the drain epitaxial layer. In this study, the method is illustrated by determining the drain doping for six discrete power MOSFET device types from three different manufacturers     

Integrated direct-coupled gyrator

An integrated gyrator is described. The device uses 1 diode, 12 resistors and 9 transistors, two of which are lateral p-n-p. Experimental results on gyration resistance, input impedance and resonant-circuit Q factor show excellent agreement with theory.     

Leakage current mechanisms in sub-50 nm recess-channel-type DRAM cell transistors with three-terminal gate-controlled diodes

We investigated the leakage mechanism in the recently developed DRAM cell transistors having deeply recessed channels for sub-50 nm technology using a gate-controlled diode method. The identification and modeling of the various leakage components in DRAM cell transistors with three-dimensional structures is of great importance for the estimation of their data retention characteristics. Our study reveals that there is a significant difference in the leakage mechanisms of planar and recessed channel MOSFETs, due to their different geometrical aspects. The leakage current at the extended gate-drain overlapping region in recessed channel MOSFETs is of particular importance from the viewpoint of their refresh modeling. The information on the leakage characteristics of three-dimensional DRAM cell transistors obtained herein will be very useful for refresh modeling and future DRAM device designs.     

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under static and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are regarded, exploited and optimised.     

Distortion cancellation in an unbalanced differential amplifier

In a differential amplifier in which the two transistors arc matched and carry the same quiescent current the second harmonic distortion generated by the emitter-base diode is exactly cancelled. When unequal currents are taken by the two transistors the cancellation is much reduced. It is shown here that the choice of a suitable current source resistance allows the cancellation condition to be restored in the unbalanced case.     

A Novel Self-Pinching Gate Biasing Scheme for Safe Operation and Characterization of GaN HEMTs

This letter presents a novel gate bias configuration for GaN HEMTs that ensures a safe operation of this kind of device by protecting the gate from forward turn-on. The bias circuit includes a simple series diode in the dc path that blocks any positive current from the gate, in other words it restricts the gate diode of the device to operate in forward bias. The new bias circuit ensures a safe operating condition of FET/HEMT transistors during forward turn-on while not hampering or degrading performance under normal operating condition.