一种快速高效的二维一级小波变换的硬件实现

提出了一种针对9/7小波滤波器的二维一级小波变换的硬件平台,整体结构采用流水方式实现,数据分组输入,列变换采用多个小波变换单元,行变换模块为可重构硬件结构,行列变换之间不需要片上存储器。与已有结构相比,该结构可以通过更少的硬件资源消耗获得更高的处理速度。     

自适应小波变换更新滤波器的优化研究

基于提升格式的小波变换被称为第二代小波变换,该种结构提供了一种灵活构造非线性小波分解和重构的方法.G.Piella根据提升格式小波变换的结构特点,提出了一种不需要额外附加信息就可完成精确重构的自适应更新滤波器,但算法只说明了滤波器系数需要满足精确重构的条件,没有具体说明如何确定滤波器的系数.在先选定预测滤波器的基础上,...     

基于开关电流双线性积分器的IFLF小波滤波器设计

根据连续时间滤波器设计理论,提出了一种基于开关电流双线性积分器和IFLF结构的取样数据小波滤波器设计方法。利用麦克劳林级数逼近小波频域函数,采用开关电流双线性积分器作为基本单元设计出传递函数为频域逼近函数的IFLF结构小波滤波器。通过调节滤波器时钟频率获得任意尺度小波函数实现连续小波变换。实验结果表明了该方法设计小波滤波器具有电路结构简单,小波函数尺度易于调节,通带灵敏度低的特点。     

基于方向正交小波基的声源定位

引入一种光滑性可调的对信号的方向性敏感的周期基插值小波,先对其进行正交化处理,构成二维空间的方向正交小波基,同时对相应的滤波器周期化,给出了快速方向小波变换的算法。对于方向性弱的声音信号可以选择阶数相对高的周期基插值小波来分析,而对于方向性强的信号只要阶数低的周期基插值小波就可以。用传声器阵列对声音信号进行采集,对采集的数据进行快速方向正交小波变换,通过角度和半径方向的图,得到两条比较清晰的半径线,它们的交点唯一确定声源的位置。     

多小波图像编码中前置滤波器的设计

本文研究多小波图像编码中前置滤波器的设计,多小波变换矢得滤波,普通的标量信号要通过一个前置滤波器转化为一信号,才能进行我小波变换。本文根据图像信号的特点,结合现有的二种前置滤波器,提出了一种新的置滤波方程。实验数据表明,这种新的前置滤波器优于现有的二种前置滤波器,因而为提高图像压缩比例创造了条件。     

超声波流量计的测量噪声滤波方法研究

针对超声波流量计容易受到外界干扰影响的问题,在超声波流量计的结果处理中引入了滤波算法。通过对工程中常用的卡尔曼滤波和小波变换两种降噪方法的分析,设计了卡尔曼滤波器和小波变换滤波器,并将两种滤波方法在超声波流量计中进行对比分析。实验结果分析表明,卡尔曼滤波器在超声波流量计的测量信号处理中具有更好的降噪性能,从而使超声波流量计具有较高的测量精度,而且更加稳定可靠,具有实用意义。     

三维存储器的存储单元形状对其性能的影响北大核心

简要介绍了三维存储器出现的背景和几种得到广泛关注的三维存储器;建立模型分析了位成本缩减(BiCS)、垂直堆叠存储阵列(VSAT)和垂直栅型与非闪存阵列(VG-NAND)三种代表性的三维存储器的存储单元的形状对其性能的影响,从理论分析的角度比较了三种存储单元结构对其存储性能的影响;采用Sentaurus软件对三种存储单元的性能进行仿真,从编程/擦除时间、存储窗口和保持性能三个方面比较了三种存储单元结构的存储性能。理论分析结果和仿真结果都一致地表明BiCS结构的圆柱孔形存储单元比其他两种存储单元更有优势。     

小波变换开关电流电路CAD设计

用开关电流技术实现小波变换,关键是小波滤波器的实现;小波滤波器传输表达式可通过对小波基函数的有理逼近来获得。基于Padé逼近的方法,采用高斯函数族作为小波基函数,对所选的高斯函数进行频域的有理分式逼近来获取小波滤波器传输表达式,从数学上提出一种设计小波变换开关电流(SI)滤波器的CAD方法。结合SI的电流模信号特点,利用双二次滤波器的性质,用SI单元电路的级联结构来实现电路的灵活设计。设计举例给出了设计思路,MATLAB仿真结果显示这种方法的可行性。     

自适应的基于Gabor函数的指纹图像增强算法

针对实际应用时采集的指纹库中指纹图像纹线粗细和质量差别很大的情况,提出了一种根据纹线宽度自适应地决定Gabor滤波器变换窗大小的指纹图像增强算法.改进了方向图的算法,在小波变换之后的低频子图上进行方向估算.实验结果表明,基于低频于图计算方向图使得运算速度和结果准确性均有提高,尤其对于低质量的指纹图像因为小波变换滤除噪声的作用,方向图准确性提高更为明显;自适应决定变换窗大小使Gabor滤波器能更好地发挥连接断线和分离粘连的作用,处理过粗或过细指纹时更具优越性.     

正交小波变换的格形滤波器实现

正交小波变换可归结为滤波器组的分析和设计,进而便于ＶＬＳＩ的实现。文中将正交格形滤波器用于实现滤波器组结构内部的正交小波变换,并提出了在独立参数空间中,每个参数仅用一个正交μ－循环逼近的格形滤波器结构,它简单,有效,便于ＶＬＳＩ实现。     

A high-throughput,memory efficient architecture for computing the tile-based 2D discrete wavelet transform for the JPEG2000

In this paper, the design and implementation of an optimized hardware architecture in terms of speed and memory requirements for computing the tile-based 2D forward discrete wavelet transform for the JPEG2000 image compression standard, are described. The proposed architecture is based on a well-known architecture template for calculating the 2D forward discrete wavelet transform. This architecture is derived by replacing the filtering units by our previously published throughput-optimized ones and by developing a scheduling algorithm suited to the special features of our filtering units. The architecture exhibits high-performance characteristics due to the throughput-optimized filters. Also, the extra clock cycles required due to the tile-based version of the discrete wavelet transform are partially compensated by the proper scheduling of the filters. The developed scheduling algorithm results in reduced memory requirements compared with existing architectures.     

A VLSI architecture for lifting-based forward and inverse wavelettransform

We propose an architecture that performs the forward and inverse discrete wavelet transform (DWT) using a lifting-based scheme for the set of seven filters proposed in JPEG2000. The architecture consists of two row processors, two column processors, and two memory modules. Each processor contains two adders, one multiplier, and one shifter. The precision of the multipliers and adders has been determined using extensive simulation. Each memory module consists of four banks in order to support the high computational bandwidth. The architecture has been designed to generate an output every cycle for the JPEG2000 default filters. The schedules have been generated by hand and the corresponding timings listed. Finally, the architecture has been implemented in behavioral VHDL. The estimated area of the proposed architecture in 0.18-μ technology is 2.8 nun square, and the estimated frequency of operation is 200 MHz     

An Efficient Pipeline Architecture and Memory Bit-Width Analysis for Discrete Wavelet Transform of the 9/7 Filter for JPEG 2000

In this paper, we propose an efficient pipeline architecture for the DWT 9/7 filter defined in JPEG 2000. The proposed architecture is composed of column and row processors to perform the separable 2-D DWT. Based on the rescheduling DWT algorithm, we derive a new data flow graph to shorten the critical path. The proposed 1-D column processor requires less pipeline registers to achieve about the same critical path compared with other lifting-based architectures. For the row processor, the data dependency of each lifting step is reduced to only two computation nodes and therefore more pipeline registers can be applied to achieve higher processing speed without increasing the internal memory size in the 2-D case. That is, for an N × N image, it only requires 4N internal memory to perform the row-wise transform. For the memory bit-width analysis, we use software simulation to reduce the memory bit-width for various compression ratios. Since a portion of information from least significant bits of DWT coefficients would be discarded after EBCOT-tier2 processing, one can decrease the data width of internal memory to perform various compression ratios of JPEG 2000 coding, especially at the low-bit rates. Our simulation results suggest that it is practically possible to design the energy-aware memory architecture to further reduce the power consumption in the future work.     

Multiplierless, Folded 9/7– 5/3 Wavelet VLSI Architecture

This brief proposes a multiplierless VLSI architecture for the famous 9/7 wavelet filters. The novelty of this architecture is the possibility to compute the 5/3 wavelet results into the 9/7 data path with a reduced number of adders compared to other solutions. The multiplierless architecture has been characterized in terms of performance through simulations into a JPEG2000 environment and compared to other solutions. Implementation on a 0.13-mum standard cell technology shows that the proposed architecture compared to other multiplierless architectures requires a reduced amount of logic with excellent performance.     

整数5/3小波变换的VLSI结构设计

在JPEG 2000中,无损图像压缩是采用整数5/3小波变换实现的.JPEG 2000也给出了5/3小波基于提升方法的算法.对提升方法的整数5/3小波变换算法进行了研究,针对二维的变换提出一种VLSI结构.该结构由4个模块构成,模块之间并行运行,模块内部采用流水线技术.对多级变换,级间的运算还可交叉,体现了提升方法的优势,较大地提高了硬件效率.其主要优点是消耗资源少且运算速度高,同时也适用于其他整数小波变换.     

JPEG2000中DWT-EBCOT联合的高效低存储VLSI结构

针对JPEG2000硬件实现中小波变换与编码之间占用大量存储的问题,该文提出一种基于码块的存储方案。通过对码块大小片内存储最大程度的复用以及对其高效简单的调度控制,从面积和功耗两方面减小了硬件实现的开销。在实现中,采用基于行的提升变换结构和比特平面并行的编码方式,提高了效率,确保整个过程的实时处理。实验结果表明：在实时编码要求下,对分辨率为512512的图像分片进行四级9/7或者5/3小波分解,码块大小为3232,采用本文结构所用的存储量与直接使用外部存储器的方法相比可减少80%以上。整个结构已通过FPGA验证,且系统时钟可以工作在100MHz。     

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations

This paper proposes two JPEG 2000 compliant architectures: one for DWT (Discrete Wavelet Transform) and one for IWT (Integer Wavelet Transform) implementation. First of all some theoretical issues about DWT and IWT are discussed, then, starting from transforms characteristics, the architectures are presented showing both performance and cost. In the literature many DWT architectures have been proposed; our implementation is a new architecture that computes the DWT using filters of interest for the forthcoming JPEG 2000 standard. Moreover, we propose a Lifting Scheme based architecture for IWT, JPEG 2000 compliant too. The proposed architectures are able to support real-time streams: the DWT one, which is made of 20,000 cells, with an input throughput of 160 Msamples per second and a clock frequency of 160 MHz, the IWT one, consisting of 50,000 cells, with an input throughput of 4.5 Msamples per second and an internal clock frequency of 108 MHz.     

JPEG2000并行阵列式小波滤波器的VLSI结构设计

提出一种基于提升算法实现JPEG2000编码系统中的二维离散小波变换(Discrete Wavelet Transform)的并行阵列式的VLSI结构设计方法.利用该方法所得结构由两个行处理器,一个列处理器以及少量行缓存组成;行列处理器内部是由并行阵列式的处理单元组成;能使行和列滤波器同时进行滤波,用优化的移位加操作替代乘法操作.整个结构采用流水线的设计方法处理,在保证同样的精度下,大大减少了运算量和提高了硬件资源利用率,几乎达到100％,加快了变换速度,也减少了电路的规模.该结构对于N×N大小的图像,处理速度达到O(N²/2)个时钟周期.二维离散小波滤波器结构已经过FPGA验证,并可作为单独的IP核应用于正在开发的JPEG2000图像编解码芯片中.     

JPEG2000实时截断码率控制新算法及其VLSI结构设计

提出一种实时编码实时截断的码率控制算法.它根据已分解的小波子带内码块有效位平面数来预测未分解的小波子带内码块有效位平面数,并根据编码通道数和小波/量化权系数为当前编码码块分配码率.并提出一种JPEG2000编码实时截断,两级码率控制的编码体系结构.第一级采用本文提出的算法实时截断码流和编码通道.第二级在低码率下采用JPEG2000标准的PCRD优化算法搜索精确的分层截断点.在最优分层截断之前多数码流和编码通道被预先截断,存储器损耗小,实时性高.低码率下,图像质量跟JPEG2000标准一致.     

A VLSI architecture of JPEG2000 encoder

This paper proposes a VLSI architecture of JPEG2000 encoder, which functionally consists of two parts: discrete wavelet transform (DWT) and embedded block coding with optimized truncation (EBCOT). For DWT, a spatial combinative lifting algorithm (SCLA)-based scheme with both 5/3 reversible and 9/7 irreversible filters is adopted to reduce 50% and 42% multiplication computations, respectively, compared with the conventional lifting-based implementation (LBI). For EBCOT, a dynamic memory control (DMC) strategy of Tier-1 encoding is adopted to reduce 60% scale of the on-chip wavelet coefficient storage and a subband parallel-processing method is employed to speed up the EBCOT context formation (CF) process; an architecture of Tier-2 encoding is presented to reduce the scale of on-chip bitstream buffering from full-tile size down to three-code-block size and considerably eliminate the iterations of the rate-distortion (RD) truncation.