基于AD9858的宽带正交信号产生技术的研究

在正交调制与解调等许多电路中,都需要一对正交的信号.而传统的正交信号的产生方法都存在很多弊端,因此选用内部时钟可高达1 GHz的高性能直接数字合成芯片AD9858作为核心器件,采用FPGA控制AD9858的设计方案产生高达400 Hz的宽带正交信号.同时详细阐述了用该方法产生正交信号的原理、硬件电路设计及调试.     

Optimized design of a digital I/Q demodulator suitable for adaptive pre-distortion of 3rd generation base station PAs

This article presents an optimized design of a high-speed digital I/Q demodulator intended for the implementation of the feedback path of an adaptive base band digital pre-distorter (DPD). Indeed, the optimization of the DPD linearization capability, in terms of correction bandwidth and nonlinearity effects minimization, is directly related to the accuracy and speed of the I/Q demodulator. In this work, a digital I/Q demodulator is designed, optimized and implemented in a Xilinx FPGA device. This allowed for high-speed processing of about 200 MHz with a substantial reduction in the FPGA used gates.     

A digital signal processor for an ANSI standard ISDN transceiver

The digital signal processing chip of a two-chip ISDN (integrated services digital network) basic access transceiver based on the ANSI standard 2B1Q code is described. Nonlinear echo cancellation is used to improve the loop coverage. The chip features a multiprocessor architecture, where each processor is optimized for the algorithm used. Full observability of internal signals and adaptive filter coefficients is supported. The device is fabricated in a 1.25-μm double-level-metal CMOS process with an active area of 47 mm²     

A 400-Ms/s frequency translating bandpass sigma-delta modulator

A bandpass Σ-Δ modulator is described in this paper that uses frequency translation inside the Σ-Δ modulator loop to take advantage of the attributes of both continuous-time and discrete-time circuits. A CMOS direct-conversion modulator digitizes a 200 kHz intermediate-frequency signal centered at 100 MHz and produces baseband I/Q outputs with a peak signal-to-noise ratio of 54 dB. Images due to I/Q mismatches are suppressed by 50 dB. This 0.35-μm digital CMOS chip operates from a 2.7/3.3-V supply, dissipates 330 mW, and occupies 3.2 mm²     

A 300-MHz quadrature direct digital synthesizer/mixer in 0.25-/spl mu/m CMOS

A 300-MHz quadrature direct digital frequency synthesizer/complex mixer (QDDSM) chip is presented. With a 32-bit input frequency control word, the tuning resolution is 0.07 Hz at the operating frequency of 300 MHz. The 12-bit I and Q inputs and 13-bit I and Q outputs offer a spurious-free dynamic range of 90.3 dB. The tuning latency is 13 clock cycles, which corresponds to 43 ns at 300 MHz. The tuning bandwidth (half the operating frequency) is 150 MHz. The IC is realized in 0.25-/spl mu/m TSMC CMOS technology with 4180 standard library cells and occupies a core area of 0.36 mm/sup 2/. At 300 MHz, the power dissipation is less than 400 mW. A key feature of the design is the creation of conditionally negating multipliers.     

Low-power broadband quadrature signal generator based on phase-tunable dividers

This paper presents the design and experimental results of a low-power 300–960 MHz I/Q signal generator for low-IF receivers. The circuit is based on phase-tunable dividers and uses delay-locked loops, which provide phase accuracy for the quadrature signals as well as low-sensitivity of the phase error against temperature and power supply variations. Thanks to the adopted technique, the phase error can be further reduced by trimming the reference voltage of the delay-locked loops through a calibration digital word, which can be stored in a non-volatile memory during manufacturing. The I/Q generator exhibits an absolute phase error before calibration that is lower than 1.5°. The I/Q phase drift due to temperature variations from ?40 to 85 °C and power supply variations from 1.1 to 1.3 V is 0.3° and 0.2°, respectively. By dividing the overall frequency range into four 165-MHz wide sub-bands and using only four 5-bit calibration words, the I/Q phase variation with respect to frequency, temperature, and power supply is lower than 1° in the 300–960 MHz operating band. The I/Q generator is implemented in a 90-nm CMOS technology and exhibits a current consumption as low as 0.5 mA.     

A 2.4–2.5 GHz WLAN Direct-Conversion Receiver Front-End With Low-Distortion Baseband Filters

Low-distortion I/Q baseband filters interface with a 2.5 GHz RF receiver front-end configured as a Gm-cell in a direct-conversion architecture targeted towards WLAN 802.11b application. The active I/Q current-mode filters use AC current to carry the large swing of both desired and blocker signals, relaxing the voltage headroom requirement to a 1.2 V supply. An on chip master–slave automatic tuner is used to lock the filter bandwidth to a precision 20 MHz reference crystal oscillator, resulting in a $≪ ,$3% tuning accuracy and $≪, $ 0.5% I/Q bandwidth matching. The receiver achieves a 3.2 dB DSB NF, ${-}$14 dBm out-of-band IIP3, and ${+}$ 27 dBm worst case IIP2, all referred to the LNA input, while drawing 30mA from a 2.7 V supply. The chip is fabricated in a 0.5 $mu$m 46 GHz $f_{T}$ SiGe BiCMOS process. The active area is 2.54 mm$^{2}$ .      

A 10-bit 20-MHz two-step parallel A/D converter with internal S/H

A 10-bit 20-MHz A/D converter for high-quality video systems such as high-definition television, video tape recorders for business use, and digital video cameras is described. This LSI circuit uses a standard two-step parallel architecture, includes automatic gain adjustment and digital two-bit error correction, and has a sample-and-hold circuit on the chip. It is fabricated by a 4.5-GHz f_T. 3-μm-rule standard bipolar technology. Its die size is 25 mm² , and its power consumption is 900 mW, which is about half of the lowest values reported to date. The converter can digitize video signals of up to 8.5 MHz at a conversion frequency of 20 MHz. The error in differential gain is 0.5 percent, and the error in differential phase is 0.5°     

一种高精度便捷式全数字示波器的设计

设计制作了一台便捷式数字示波器,能对小于20 MHz的任意周期的赫兹信号进行频率、幅值测量,同时也能对信号波形实时显示。该示波器以数字信号处理器TMS320 VC33和可编程逻辑器件EPF10K50V为核心,以OP37进行信号预处理,再由A/D芯片AD7667完成信号采集,通过总线将信号传输给主处理器,采用LJD-ZN-3200K智能终端设备实现人机交互,具有对周期信号进行测量、连续和单次触发及存储等功能,并可对被测信号无失真显示。系统测试结果表明,系统频率测量误差小于0.05%,信号幅值测量误差小于1%。     

A micropower CMOS, direct-conversion, VLF receiver chip formagnetic-field wireless applications

A micropower CMOS, direct-conversion very low frequency (VLF) receiver is described for receiving low-level magnetic fields from resonant sensors. The single-chip, phase locked loop (PLL)-synthesized receiver covers a frequency range of 10-82 kHz and provides both analog and 9-b digital baseband I and Q outputs. Digital I and Q outputs are accumulated in a companion digital chip which provides baseband signal processing. Emphasis is plated on the receiver micropower RF preamplifier which uses a lateral bipolar input device because of the significant increase in flicker noise illustrated for PMOS devices in weak inversion. Lateral bipolar transistors are also utilized in the mixer and IF stages for low flicker noise and low dc offsets. Special attention is given to isolating the internal local oscillator signals from the low-level RF input (0.3 μV noise floor in 300 Hz BW), and local oscillator feedthrough is indiscernible in the RF preamplifier output noise spectrum. The 100% duty-cycle receiver, intended for miniature, battery-operated wireless applications, operates approximately four months at 80 μA from a 6-V, 220-mA-hr battery     

Cascaded Complex ADCs With Adaptive Digital Calibration for $I/Q$ Mismatch

A complex analog-to-digital converter (ADC) intended for digital intermediate frequency (IF) receiver applications digitizes analog signals at IFs with excellent power/bandwidth efficiency. However, it is vulnerable to mismatches between its in-phase and quadrature (I/Q) paths that can dramatically degrade its performance. The proposed solution mitigates I/Q mismatch effects using a complex sigma-delta (SigmaDelta) modulator cascaded with 9-bit pipeline converters in each of the I and Q paths. The quantization noise of the first stage complex modulator is eliminated using an adaptive scheme to calibrate finite-impulse response digital filters in the digital noise-cancellation logic block. Although low-pass SigmaDelta cascade ADCs are widely used because of their inherent stability and high-order noise shaping, the complex bandpass cascade architecture introduced herein maintains these advantages and doubles the noise shaping bandwidth. Digital calibration also reduces the effects of analog circuit limitations such as finite operational amplifier gain, which enables high performance and low power consumption with high-speed deep-submicrometer CMOS technology. Behavioral simulations of the complex SigmaDelta/pipeline cascade bandpass ADC using the adaptive digital calibration algorithm predict a signal-to-noise ratio (SNR) of 78 dB over a 20-MHz signal bandwidth at a sampling rate of 160 MHz in the presence of a 1% I/Q mismatch.     

A Complex Image Rejection Circuit With Sign Detection Only

In direct-conversion receivers, radio frequency (RF) signals are down-converted to low or zero intermediate frequency (IF) using complex in-phase and quadrature (I/Q) mixers with no prior image filtering. Due to I/Q path gain and phase errors, image leaks into the signal band during the down-conversion process. A generic image rejection algorithm is proposed to reject image in the baseband using a zero-forcing sign-sign adaptive feedback concept. The orthonormal property of complex I/Q channels is exploited to update their gain and phase errors by detecting only four signs, and image is corrected with four multiplications and two additions. The proposed image rejection algorithm can be implemented in a digital, analog, or hybrid form. A complex baseband sample and hold (S/H) with a digital error detector, which is a hybrid example, achieves an image rejection of 65 dB while sampling at 40 MS/s. The prototype chip fabricated in 0.18-mum CMOS occupies 800times450 mum², and consumes 23 mW at 1.8 V     

A PLL based WSN transmitter and I/Q LO signal generator at 430–435 MHz

A fully integrated Phase-Locked Loop (PLL) based transmitter and I/Q Local Oscillating (LO) signal generator used for half-duplex Wireless Sensor Networks (WSN) transceivers is proposed. Instead of one 430–435 MHz PLL for frequency synthesizing, a 1.72–1.74 GHz PLL is designed together with a 1/4 frequency divider. Then the chip area of the inductors in the Voltage-Controlled Oscillator (VCO) is decreased to about 1/16, and I/Q dual-path LO signals can be obtained without additional power consumption. A Gray-code controlled prescaler is proposed to avoid the glitches and uncertain states, and then the frequency dividing accuracy is improved by 17%. A Gauss Frequency Shift Keying (GFSK) transmitter with a pipeline modulator is proposed, the 1st and 2nd Adjacent Channel Power Ratio (ACPR) are −19.9 and −20.7 dBc, respectively. A mathematical spur model of 1/4 frequency dividers is built here, and then a low-spur 1/4 frequency divider composed of our proposed improved Current Mode Logic (CML) latches is designed. The testing results show that the reference spurs are −61.2 dBc@20 MHz and −57.7 dBc@40 MHz at the output of the PLL, and −70.5 dBc@20 MHz and −66.6 dBc@40 MHz at the output of our 1/4 divider. With 2.6-mW power consumption, our proposed 1/4 frequency divider has a phase-noise contribution of only 0.5 dBc/Hz@500 kHz and 0.2 dBc/Hz@1 MHz.     

A 1-MHz-bandwidth second-order continuous-time quadrature bandpass sigma-delta modulator for low-IF radio receivers

This paper presents a quadrature bandpass /spl Sigma//spl Delta/ modulator with continuous-time architecture. Due to the continuous-time architecture and the inherent anti-aliasing filter, the proposed /spl Sigma//spl Delta/ modulator needs no additional anti-aliasing filter in front of the modulator in contrast to quadrature bandpass /spl Sigma//spl Delta/ modulators with switched-capacitor architectures. The second-order /spl Sigma//spl Delta/ modulator digitizes complex analog I/Q input signals at 1-MHz intermediate frequency and operates within a clock frequency range of 25-100 MHz. The modulator chip achieves a peak signal-to-noise-distortion ratio (SNDR) of 56.7 dB and a dynamic range of 63.8 dB within a 1-MHz signal bandwidth and at a clock frequency of 100 MHz. Furthermore, it provides an image rejection of at least 40 dB. The 0.65-/spl mu/m BiCMOS chip consumes 21.8 mW at 2.7-V supply voltage.     

A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

A receiver for SRDs implemented by the 0.35μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of--60 dBm and a control gain of 60 dB. The S<,11> reaches-20 dB at 433 MHz and-10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.     

An 800-MHz quadrature digital synthesizer with ECL-compatibleoutput drivers in 0.8 μm CMOS

An 800 MHz quadrature direct digital frequency synthesizer (QDDFS4) chip is presented. The chip synthesizes 12 b sine and cosine waveforms with a spectral purity of -84.3 dBc, The frequency resolution is 0.188 Hz with a corresponding switching speed of 5 ns and a tuning latency of 47 clock cycles. The chip is also capable of frequency and phase modulation. ECL-compatible output drivers are provided to facilitate I/O compatibility with other high speed devices. A high gain amplifier at the clock input enables the QDDFS4 chip to be clocked with ac-coupled RF signal sources with peak-to-peak voltage swings as small as 0.5 V. The 0.8 μm triple level metal N well CMOS chip has a complexity of 94000 transistors with a core area of 5.9×6.7 mm². Power dissipation is 3 W at 800 MHz and 5 V     

A monolithic digital chirp synthesizer chip with I andQ channels

A monolithic digital chirp synthesizer (DCS) chip has been developed using GaAs/AlGaAs HI²L technology. The 6500-HBT-gate DCS chip is capable of producing linear frequency-modulated (chirp) waveforms or single-frequency waveforms. The major components of the DCS are two 28-b pipelined accumulators, a 1.8 kb sine ROM, a 1.8 kb cosine ROM, and two 8 b digital-to-analog converters (DACs). The total chip area is 4.877 mm×6.172 mm using a minimum feature size of 1.5 μm. All components of the DCS are fully functional and the device has been clocked to 450 MHz with a power dissipation of 18 W     

Ka-band analog front-end for software-defined direct conversion receiver

A six-port Ka-band front-end architecture based on direct conversion for a software-defined radio application is proposed in this paper. The direct conversion is accomplished using six-port technology. In order to demodulate various phase-shift-keying/quadrature-amplitude-modulation (PSK/QAM) modulated signals at a high bit rate, a new analog baseband circuit was specially designed according to the I/Q equations presented in the theoretical part. An experimental prototype has been fabricated and measured. Simulation and measurement results for binary PSK, quaternary PSK (QPSK), 8 PSK, 16 PSK, and 16 QAM modulated signals at a bit rate up to 40 Mb/s are presented to validate the proposed approach. A software-defined radio can be designed using the new front-end and only two analog-to-digital converters (ADCs) because the I/Q output signals are generated by analog means. Previous six-port receivers make use of four ADCs to read the six-port dc levels and require digital computations to generate the I/Q output signals. With the proposed approach, the load of the signal processor will therefore be reduced and the modulation speed can be significantly increased using the same digital signal processor.     

一种基于MATLAB+正交上变频的模拟通信信号设计方法

文中提出了一种利用MATLAB 产生模拟通信信号的基带I/ Q 调制数据,通过FPGA+DAC 数字正交上变频来实现中频模拟通信信号产生的设计方法。该方法实现电路简单,不需要专门的模拟器件。通过该方法来实现模拟通信信号的产生,为构建更加复杂的电磁环境,实现雷达电子战和通信电子战领域的交织融合提供了有力保障,具有很强的实用价值。     

A wide-range programmable frequency synthesizer based on a finite state machine filter

In this article, an FPGA-based design and implementation of a fully digital wide-range programmable frequency synthesizer based on a finite state machine filter is presented. The advantages of the proposed architecture are that, it simultaneously generates a high frequency signal from a low frequency reference signal (i.e. synthesising), and synchronising the two signals (signals have the same phase, or a constant difference) without jitter accumulation issue. The architecture is portable and can be easily implemented for various platforms, such as FPGAs and integrated circuits. The frequency synthesizer circuit can be used as a part of SERDES devices in intra/inter chip communication in system-on-chip (SoC). The proposed circuit is designed using Verilog language and synthesized for the Altera DE2-70 development board, with the Cyclone II (EP2C35F672C6) device on board. Simulation and experimental results are included; they prove the synthesizing and tracking features of the proposed architecture. The generated clock signal frequency of a range from 19.8?MHz to 440?MHz is synchronized to the input reference clock with a frequency step of 0.12?MHz.