一种数字信号处理器的动态功耗管理方案

动态功耗管理是一种系统级低功耗设计技术，降低功耗的思路是根据系统当前负载动态调整时钟频率或者关闭时钟。文章以数字信号处理器为模型，提出了一种系统属性可调节的动态功耗管理方案，它支持通过软硬件配合对功耗进行灵活的动态管理，其管理策略采用了适应性预测算法，并引入非确定性因子。实验结果表明，该方案可以大大降低数字信号处理器的功耗。     

面向国产UniCore的安卓系统动态变频低功耗策略

基于自主设计的国产UniCore嵌入式平台,分析了安卓电源管理和软件层面的动态变频低功耗技术.在此基础上,提出一种动态变频架构,设计实现了动态时钟供给、动态变频的内核层和驱动层,并对传统的动态变频策略进行改进,使其能够适应不同的应用环境.给出了LCD背光调整、单个设备休眠/唤醒等其他系统运行态低功耗技术.实验结果表明,采用功耗管理技术,系统极限运行功耗为全速运行时的45％,安卓系统运行功耗明显降低.     

通用视频输出控制器IP核的低功耗设计

随着芯片的集成度越来越高,芯片的功耗成为芯片设计中越来越重要的优化参数。设计了一种可应用于视频处理芯片、多媒体手持设备、嵌入式SoC等系统中的视频输出控制器。设计中通过多种工艺无关的低功耗设计技术优化控制器的动态功耗。首先分析各子模块的工作频率,降低低速子模块的工作时钟,然后通过添加门控时钟单元降低时钟的翻转次数。应用Design Compiler[1]进行工程的功耗分析,结果表明设计中使用的低功耗设计方法有效降低了模块的动态功耗。     

一种适用于SoC的时钟复位管理电路设计

给出了一套适用于SoC芯片的时钟和复位管理电路设计范例,详细介绍了SoC芯片中的时钟和复位管理电路的实现方案。其中时钟管理电路支持输入时钟可选、PLL动态变频、时钟门控管理和时钟状态查询功能,能够灵活的控制各模块输入时钟开启或关闭,很好的支持SoC芯片低功耗工作模式。复位管理电路支持复位输入控制功能和复位状态查询功能。复位输入控制可以选择使能或不使能复位源触发系统复位。     

基于SOC的低功耗管理模块设计

功耗是片上系统(SOC)设计中的关键指标之一。对于SOC芯片的低功耗设计,可以采用多种设计方法进行优化。本文设计的低功耗管理模块是通过管理工作时钟的方式对SOC的功耗进行动态调节,能够有效地降低SOC芯片的功耗。     

基于SoC低功耗MMC卡控制器的设计

本文基于最新的MMC4.1协议,设计了一款基于AHB总线的低功耗MMC卡控制器.设计采用了高性能改进异步FIFO.针对MMC卡常用于便携式产品中的低功耗需求,采用了动态功耗管理和门控时钟技术,可降低功耗约60%;探讨了一种基于SoC高性能接口控制器电路通用体系架构,已成功应用到多种接口控制器的设计中.设计通过了仿真(NC-Verilog)、综合(DC)以及FPGA验证,嵌入到单板系统中,实现了与MMC存储卡之间的数据传输.     

超深亚微米数字电路的低功耗设计

随着集成电路逻辑复杂度日益提高,而工艺尺寸进入了超深亚微米数量级,低功耗设计已经成为整个SOC设计中关键的问题之一.电源电压是影响功耗的最重要因素,而阈值电压、体偏压和时钟频率也对功耗有影响.目前,对于数字电路,已经研发出一些有效地进行功耗管理,降低功耗的技术,并已应用于具体项目中.本文首先综述性地介绍几种低功耗设计方法,包括:多阈值电压CMOS技术;多电源电压;门控时钟;动态电压频率调制;动态体偏压调制;加入电源门控、以及状态可保持的电源门控技术,并逐一讨论了它们对降低功耗的具体作用.最后,针对最新的基于通用功耗格式的状态保持电源门控技术,本文概述其实现步骤.     

可进一步降低功耗的先进的时钟管理技术

为满足低功耗市场的要求,许多类型的电子器件都采用了时钟管理技术。微处理器利用多种省电模式(如睡眠、打盹或休眠模式)来降低功率消耗。一些可编程逻辑器件(CPLD/FPGA)利用省电技术来降低动态功率损耗。但不     

新品秀场

杭州晟元芯片技术有限公司的AS300--动态令牌(OTP)专用芯片主要特征：超低功耗,深度休眠功耗<0.6uA,片上集成了800KHz的环振,休眠模式可使用32.768KHz时钟,以降低系统动态功耗,32位单周期乘法指令,支持国密SM3算法,多种外设接口。Deep休眠模式：RTC工作,系统时钟32.768KHz,CPU停止工作,LCDC不工作,高速运行模式：RTC工作,系统时钟800KHz,CPU全速运行SM3算法,LCDC全显输出。     

利用实时时钟降低嵌入式系统功耗

众所周知,当嵌入式系统进入IDLE状态,CPU可以进入到低功耗模式,系统功耗会降低。但在一般的嵌入式系统中,当系统进入IDLE状态后,即使没有其他设备中断,实时时钟中断也会不断唤醒CPU,这样就会大大增加系统的功耗。本文通过对实时时钟系统的修改,延长了实时时钟中断间隔,使CPU长时间处于低功耗模式,从而大大降低了系统功耗。     

Dual-threshold voltage techniques for low-power digital circuits

Scaling and power reduction trends in future technologies will cause subthreshold leakage currents to become an increasingly large component of total power dissipation. This paper presents several dual-threshold voltage techniques for reducing standby power dissipation while still maintaining high performance in static and dynamic combinational logic blocks. MTCMOS sleep transistor sizing issues are addressed, and a hierarchical sizing methodology based on mutual exclusive discharge patterns is presented. A dual-V_t domino logic style that provides the performance equivalent of a purely low-V _t design with the standby leakage characteristic of a purely high-V_t implementation is also proposed     

基于FPGA的低功耗高精度DPWM设计

提出了一种基于FPGA实现低功耗、高分辨力数字脉冲调制(DPWM)的设计方案。该方案在获得高分辨力DPWM的同时降低了对系统时钟频率的要求。该方法充分利用了数字时钟管理器(DCM)的倍频及移相功能,而且使DCM模块只在开关周期的1/16工作从而减少系统的功耗。在系统时钟频率为16 MHz,开关频率为1 MHz,实现了11位分辨力的DPWM并通过了FPGA对其的仿真及验证。     

A 1.5-V-100-μW ΔΣ modulator with 12-b dynamic rangeusing the switched-opamp technique

The design and implementation of a very low supply voltage/low power ΔΣ modulator is presented. It is based on the switched-opamp technique, which allows low voltage operation with a standard process and without voltage multiplication. The design methodology is illustrated with a second-order single-loop ΔΣ modulator. The chip is implemented in a 0.7-μm CMOS process with standard threshold voltages. The power supply is 1.5 V and the power dissipation is only 100 μW. The measured dynamic range in the speech bandwidth of 300-3400 Hz is 12 b. The total harmonic distortion (THD) is lower than -72 dB     

Power dissipation analysis and optimization of deep submicron CMOSdigital circuits

This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and η, which reflects the drain induced barrier lowering, are also addressed     

Active voltage clamp in flyback converters operating in CCM mode under wide load variation

Active clamp topologies of low power dissipation have become a very attractive solution in order to limit overvoltages in flyback converters. Although many suitable topologies have been introduced for the case of discontinuous conduction mode (DCM), where the duty cycle value depends on the load level, in continuous conduction mode (CCM) it is more difficult to appropriately design such topologies so as to "sense" load changes-due to the small duty cycle divergence under wide load variation. Taking for granted that in order to achieve high power-factor correction in these converters, CCM is a more attractive mode of operation, a drastic solution for this case that will manage to eliminate voltage stresses under wide load changes has become very essential. For this purpose, this paper presents an active clamp topology with small power dissipation, suitable for flyback converters operating in CCM mode. Its main idea is the use of a load-dependent current source, consisting of an auxiliary converter operating in DCM mode. Experimental results highlight the effectiveness of the proposed topology under wide load changes, establishing it as an appropriate solution in order to develop flyback converters, even at the power range of 500 W.     

TFT-LCD驱动控制电路芯片研究

研制成功一款彩屏手机用262144色132RGB×176-dot分辨率TFT-LCD单片集成驱动控制电路芯片,提出了基于低/中/高混合电压工艺、数模混合信号VLSI显示驱动芯片的设计及其验证方法,开发了SRAM访问时序冲突解决电路、二级输出驱动电路和动态负载补偿输出缓冲电路等新型电路结构,有效减小了电路的功耗和面积,抑制了回馈电压的影响,提高了液晶显示画面质量。采用0.25μm混合电压CMOS工艺实现的工程样片一次性流片成功,整个芯片的静态功耗约为5mW,输出灰度电压的安定时间小于30μs,芯片性能指标均达到设计要求。     

Power reduction methods for NMOS dynamic random access memories

Power reduction methods for NMOS dynamic random access memories are proposed which reduce power dissipation. As the bit density increases in NMOS dynamic random access memories the power dissipation increases. A major consideration in the design of megabit dynamic random access memories is the power supply voltage. The power supply voltage mainly depends upon the following factors: power dissipation; reliability, such as high field effects due to small device size; memory cell operating margin. Power dissipation in decoders and 1 megabit NMOS dynamic random access memory chips are discussed. The basic properties of the proposed methods and a prototype VLSI implementation are discussed. In order to meet user power supply requirements, the proposed power reduction methods are useful for future megabit NMOS dynamic random access memories.     

Low-power CMOS digital design with dual embedded adaptive powersupplies

A low-power CMOS design methodology with dual embedded adaptive power supplies is presented. A variable supply-voltage scheme for dual power supplies, namely, the dual-VS scheme, is presented. It is found that the lower supply voltage should be set at 0.7 of the higher supply voltage to minimize chip power dissipation. This knowledge aids designers in the decision of the optimal supply voltages within a restricted design time. An MEPG-4 video codec chip is designed at 2.5 and 1.75 V for internal circuits that are generated from an external power supply of 3.3 V by the dual-VS circuits. Power dissipation is reduced by 57% without degrading circuit performance compared to a conventional CMOS design     

A unified design methodology for CMOS tapered buffers

In this paper, the various disparate approaches to CMOS tapered buffer design are unified into an integrated design methodology. Circuit speed, power dissipation, physical area, and system reliability are the four performance criteria of concern in tapered buffers, and each places a separate, often conflicting, constraint on the design of a tapered buffer. Enhanced short-channel tapered buffer design equations are presented for propagation delay and power dissipation, as well as a new split-capacitor model of hot-carrier reliability of tapered buffers and a two-component physical area model. Each performance criterion is individually investigated and analyzed with respect to the number of stages and tapering factor, and the interaction of the four criteria is examined to develop both a qualitative and a quantitative understanding of the various design tradeoffs. The creation of process dependent look-up tables for optimal buffer design is described, and a methodology to apply these look-up tables to application-specific tapered buffers for both unconstrained and constrained systems is developed     

低功耗SOC的动态时钟管理

介绍了一种系统级设计的时钟管理方案以及功耗管理模块的实现;分析了该方案在实现中可能存在的问题,并给出解决方法。此方案可以显著地降低时钟网络的动态功耗,弥补了现有工具只能在设计后期才能发挥作用的不足,达到了降低整个SOC芯片功耗的目的;引用具体设计项目,说明系统如何动态地调节时钟频率。