Contact Resistance in Nanocrystalline Silicon Thin-Film Transistors

Thin-film transistors (TFTs) of nanocrystalline silicon (nc-Si:H) made by plasma-enhanced chemical vapor deposition have higher electron and hole field-effect mobilities than their amorphous counterparts. However, as the intrinsic carrier mobilities are raised, the effective carrier mobilities easily can become limited by the source/drain contact resistance. To evaluate the contact resistance, the nc-Si:H TFTs are made with a range of channel lengths. The TFTs are fabricated in a staggered top-gate bottom source/drain geometry. Both the intrinsic and the - or -doped nc-Si:H source/drain layers are deposited at 80-MHz excitation frequency at a substrate temperature of 150 . Transmission electron microscopy of the TFT cross section indicates that crystallites of doped nc-Si:H nucleate on top of the Cr source/drain contacts. As the film thickness increases, the crystallites coalesce, and the leaf-shaped crystal grains extend through the doped layer to the channel i layer. The contact resistance is estimated by measuring I_DS for several channel lengths at fixed gate and drain voltages. The results show that the contact resistance depends on the gate voltage and that the source/drain current of these TFTs at V_{DS =} 10 V becomes limited by the contact resistance when the channel length is less than 10 mum for n-channel and less than 25 mum for p-channel.     

Compensated back-channel TFTs in hydrogenated amorphous silicon

Compensated back-channel inverted staggered TFTs have been made in a-Si:H. Donor impurities were implanted to form a good source and drain ohmic contact followed by an acceptor implant to compensate the channel region. TFTs have been made with no degradation of channel mobility due to the implants and a leakage current between source and drain comparable with the best TFTs made using conventional etched back-channel technology.     

Self-aligned amorphous-silicon TFTs on clear plastic substrates

We fabricated the first bottom-gate amorphous silicon (a-Si:H) thin-film transistors (TFTs) on a clear plastic substrate with source and drain self-aligned to the gate. The top source and drain are self-aligned to the bottom gate by backside exposure photolithography through the plastic substrate and the TFT tri-layer. The a-Si:H channel in the tri-layer is made only 30 nm thick to ensure high optical transparency at the exposure wavelength of 405 nm. The TFTs have a threshold voltage of /spl sim/3 V, subthreshold slope of /spl sim/0.5 V/dec, linear mobility of /spl sim/1 cm/sup 2/V/sup -1/ s/sup -1/, saturation mobility of /spl sim/0.8 cm/sup 2/V/sup -1/s/sup -1/, and on/off current ratio of >10/sup 6/. These results show that self-alignment by backside exposure provides a solution to the fundamental challenge of making electronics on plastics: overlay misalignment.     

基于高迁移率微晶硅的薄膜晶体管

近年来,微晶硅(μc-Si:H)被认为是一种制作 TFT 的有前景的材料.采用PECVD法,在低于200℃时制作了微晶硅TFTs,其制作条件类似于非晶态 TFTs.微晶硅 TFTs 器件的迁移率超过了 30 cm2/Vs,而阈值电压是 2.5 V.在长沟道器件(50～200 μm)中观测到了这种高迁移率.但对于短沟道器件(2 μm),迁移率就降低到了7 cm2/Vs.此外,该 TFTs 的阈值电压随着沟道长度的减少而增大.文章采用了一种简单模型解释了迁移率、阈值电压随着沟道长度的缩短而分别减少、增加的原因在于源漏接触电阻的影响.     

Fabrication of high-mobility p-channel poly-Si thin filmtransistors by self-aligned metal-induced lateral crystallization

High-mobility p-channel poly-Si TFTs were fabricated using a new low-temperature process (⩽500°C): self-aligned metal-induced lateral crystallization (MILC). With a one-step annealing at 500°C, activation of dopants in source/drain/gate a-Si films as well as the crystallization of channel a-Si films was achieved. The TFTs showed a threshold voltage of -1.7 V, and an on/off current ratio of ~10⁷ without post-hydrogenation. The mobility was measured to be as high as 90 cm²/V·s, which is two to three times higher than that of the poly-Si TFTs fabricated by conventional solid-phase crystallization at around 600°C     

Gated-four-probe a-Si:H TFT structure: a new technique to measurethe intrinsic performance of a-Si:H TFT

In this letter, a new technique based on gated-four-probe hydrogenated amorphous silicon (a-Si:H) thin-film transistor (TFT) structure is proposed. This new technique allows the determination of the intrinsic performance of a-Si:H TFT without any influence from source/drain series resistances. In this method, two probes within a conventional a-Si:H TFT are used to measure the voltage difference within a channel. By correlating this voltage difference with the drain-source current induced by applied gate bias, the a-Si:H TFT intrinsic performance, such as mobility, threshold voltage, and field-effect conductance activation energy, can be accurately determined without any influence from source/drain series resistances     

Low temperature poly-Si thin-film transistor fabrication bymetal-induced lateral crystallization

A new low temperature crystallization method for poly-Si TFTs was developed: Metal-Induced Lateral Crystallization (MILC). The a-Si film in the channel area of a TFT was laterally crystallized from the source/drain area, on which an ultrathin nickel layer was deposited before annealing. The a-channel poly-Si TFTs fabricated at 500°C by MILC showed a mobility of 121 cm²/V·s, a threshold voltage of 1.2 V, and an on/off current ratio of higher than 10⁶ . These electrical properties are much better than TFTs fabricated by conventional crystallization at 600°C     

A high-performance thin-film transistor with a vertical offsetstructure

In this study, we propose a novel device structure combined with conventional hydrogenated amorphous silicon (a-Si:H) for the source and drain regions and microcrystalline silicon (μc-Si:H) for the channel region to obtain a high-performance thin-film transistor (TFT). This is a vertical a-Si:H offset structure used to suppress OFF-state current to a small value which is comparable to the conventional a-Si:H TFTs with a much higher drivability. The fabrication process is simple, low temperature (⩽300°C), and low cost, with a potential for high reliability     

High-performance hydrogenated amorphous-Si TFT for AMLCD and AMOLED applications

A novel technology for manufacturing high-performance hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) is developed in this letter. In the bottom gate light-shield a-Si:H TFT structure, the side edge of a-Si:H island is capped with extra deposition of heavily phosphorous-doped a-Si layer. Such an ingenuity can effectively eliminate the leakage path between the parasitic contacts of source/drain metal and the sidewall of a-Si:H island edge. In addition, electrical performance of the novel a-Si:H TFT device exhibits superior effective carrier mobility as high as 1.05 cm/sup 2//Vs, due to the enormous improvement in parasitic resistance. The impressively high performance of the proposed a-Si:H TFT provides the potential to apply foractive matrix liquid crystal display and active matrix organic light-emitting diode technology.     

Drain-bias dependence of threshold voltage stability of amorphous silicon TFTs

Amorphous silicon (a-Si:H) thin-film transistors (TFTs) used in emerging, nonswitch applications such as analog amplifiers or active loads, often have a bias at the drain terminal in addition to the gate that can alter their threshold voltage (V/sub T/) stability performance. At small gate stress voltages (0/spl les/V/sub ST//spl les/15 V) where the defect state creation instability mechanism is dominant, the presence of a bias at the TFT drain decreases the overall shift in V/sub T/(/spl Delta/V/sub T/) compared to the /spl Delta/V/sub T/ in the absence of a drain bias. The measured shift in V/sub T/ appears to agree with the defect pool model that the /spl Delta/V/sub T/ is proportional to the number of induced carriers in the a-Si:H channel.     

Feasibility of an Ag-alloy film as a thin-film transistor liquid-crystal display source/drain material

The Ag-alloy films have been investigated as source/drain materials applicable to thin-film transistor liquid-crystal displays (TFT-LCDs). The Ag-alloy consisting of 0.9at.%Pd, 1.7at.%Cu (designated APC) showed a resistivity that was lower than one-half that of AlNd. It also had good contact characteristics with amorphous Si (a-Si). In addition, the Ag/Si was stable after heating to above 700°C, requiring no diffusion barrier to prevent reaction between Ag and Si. Pure Ag films deposited on glass by DC magnetron sputtering showed severe hillock formation, hole growth, and agglomeration upon annealing in air. In comparison, the APC-alloy film exhibited improved resistance to agglomeration. Further, inverted-staggered back-channel-etch hydrogenated amorphous silicon (a-Si:H) TFTs using an APC-alloy film as a source/drain material had a threshold voltage of 4 V. A structure of single layers of gate-APC alloys and source/drain-APC alloys leads to lower costs and productivity improvements of large-area, high-resolution, active-matrix LCDs, such as 40-in. size panels through process simplification.     

Thick-layered etched-contact amorphous silicon transistors

We introduce a new thick-layered, etched-contact a-Si:H TFT (TLEC-TFT) structure which allows the use of thick a-Si:H layers without increasing the TFT contact resistance. This device facilitates the integration of high-performance TFTs and thick-layered photo-transistors in a-Si:H-based image sensors. The TLEC-TFT is fully compatible with the conventional TFT fabrication process and requires no extra masking steps. For low values of the drain-to-source voltage, our new TFT boosts the linear region current by two orders of magnitude over that of conventional TFTs with identically thick a-Si:H layers. By removing the adverse effects of contact resistance in transistors with thick a-Si:H layers, our TLEC-TFT design allows us to compare the performance of TFTs with thick and thin a-Si:H layers. We find that the width of the conduction-band tail decreases in thick-layered a-Si:H TFTs. This reduction in the width of the band tails results in an increase in the TFT mobility and subthreshold slope. Consequently, thick-layered, etched-contact TFTs possess higher overall current-drive capabilities compared to conventional, thin-layered TFTs. We present experimental evidence which correlates the width of the conduction-band tail to the density of as-deposited free carriers     

A new a-Si:H thin-film transistor pixel circuit for active-matrix organic light-emitting diodes

We propose a new pixel circuit using hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs), composed of three switching and one driving TFT, for active-matrix organic light-emitting diodes (AMOLEDs) with a voltage source method. The circuit simulation results based on the measured threshold voltage shift of a-Si:H TFTs by gate-bias stress indicate that this circuit compensates for the threshold voltage shifts over 10000 h of operation.     

Validation of bulk-charge effect parameter extraction in MOSFETs

Our recently proposed method to extract the bulk-charge effect parameter in MOSFETs is scrutinized by studying SOI devices, a-Si:H TFTs and short- as well as long-channel bulk MOSFETs. The method requires measuring the drain current as a function of gate voltage at two small values of drain voltage chosen in the linear region of operation.     

Improvement of the reliability of amorphous silicon transistors byconduction-band tail width reduction

We present theoretical and experimental evidence showing that bias induced threshold voltage degradation of a-Si:H transistors is reduced by decreasing the width of the conduction-band tail. We show that transistors which are made using a thick (0.5 μm) a-Si:H layer possess a narrower conduction-band tail compared to transistors made using thin (0.05 μm) a-Si:H layers. We find that bias-induced threshold voltage degradation decreases by a factor of two for thick-layered TFTs compared with conventional, thin-layered TFTs. Finally, we present device design guidelines for improving the reliability of a-Si:H TFTs including several possible device designs for achieving further improvements in the reliability of a-Si:H TFTs     

The Effects of Drain-Bias on the Threshold Voltage Instability in Organic TFTs

In this letter, the influence of drain bias on the threshold voltage instability in pentacene-based organic thin-film transistors (OTFTs) was studied. By applying different drain biases to adjust the channel carrier concentration in linear mode, the threshold voltage shift was found to be proportional to the carrier concentration. The experimental data can be well quantitatively explained by the drain bias-stress theory developed for a-Si TFTs. The outcome gives the insight of the degradation mechanism of OTFTs and is important for the design of OTFT pixel circuit, OTFT analog amplifiers, or OTFT active loads.     

Stability of Amorphous-Silicon and Nanocrystalline Silicon Thin-Film Transistors Under DC and AC Stress

Bottom-gated n-channel thin-film transistors (TFTs) were fabricated using hydrogenated amorphous-silicon (a-Si:H)/ nanocrystalline silicon (nc-Si:H) bilayers as channel materials, which are deposited by plasma-enhanced chemical vapor deposition at low temperatures. The stability of these devices is investigated under static and dynamic bias stress conditions. For comparison, the stability of a-Si:H and nc-Si:H single-layer TFTs is investigated under similar bias stress conditions. The overall results demonstrate that the a-Si:H/nc-Si:H bilayer TFTs are superior compared with their counterparts of a-Si:H and nc-Si:H TFTs regarding device performance and stability.     

Hydrogen dilution effect on the properties of coplanar amorphoussilicon thin-film transistors fabricated by inductively-coupled plasmaCVD

The electrical and optical properties of the hydrogenated amorphous silicon (a-Si:H) films deposited by inductively-coupled plasma (ICP) chemical vapor deposition (CVD) with a variation of H₂ flow rate have been studied. The photosensitivity of a-Si:H is ~10⁷ when the H₂/SiH₄ ratio is between 3 and 8. With increasing H₂/SiH₄, the SiH₂ mode infrared absorption has a minimum at a H₂/SiH₄ ratio of 8. Coplanar a-Si:H thin-film transistors (TFT's) were fabricated using a triple layer of thin a-Si:H, silicon-nitride, and a-Si:H deposited by ICP-CVD using ion doping and low resistivity Ni silicide. After patterning the thin a-Si:H/silicon-nitride layers on the channel region, the gate and source/drain regions were ion-doped and then heated at 230°C to form Ni silicide layers. The low resistive Ni silicide formed on the a-Si:H reduces the offset length between gate and source/drain, leads to a coplanar a-Si:H TFT. The TFT exhibited a field effect mobility of 0.6 cm²/Vs and a threshold voltage of 2.3 V at the H₂/SiH₄ ratio of 8. The effect of H₂ dilution in SiH₄ on the coplanar a-Si:H TFT performance has been investigated. We found that the performance of the TFT is the best when the SiH₂ mode density in a-Si:H is the minimum. The coplanar TFT is very suitable for large-area, high density TFT displays because of its low parasitic capacitance between gate and source/drain contacts     

New split FET technique for measurements of source seriesresistance applied to amorphous silicon thin film transistors

A split field-effect transistor (SFET) is proposed for measuring source and drain series resistances. This device is made by splitting a conventional thin-film transistor (TFT) from the source to the drain in such a way that the gate width of each half is a linear function of the distance from the source. The analysis shows that the intrinsic current-voltage characteristics of such a device should be symmetrical with respect to the polarity of the drain-to-source voltage. Hence, the observed asymmetry of the device characteristic yields direct information about the differences between source and drain series resistances, which are inversely proportional to the contact width. For an a-Si TFT it is shown that the source series resistance is proportional to the inverse square root of the drain current in a wide range of currents. The technique can be applied to a large variety of FETs. For a-Si TFTs, it provides an accurate tool for determining the effects of contact overlap, bias stress, and temperature dependences of series resistances     

Device analysis for a-Si:H thin-film transistors with organicpassivation layer

Two dimensional device analysis has been performed to explain the experimental drain current-gate voltage (I_D-V_GS) characteristics of hydrogenated amorphous silicon thin-film transistors with various passivation layers. The shift of the I_D-V_GS curve in the negative direction and the increase of S-factor (the inverse of subthreshold slope in logarithmic I_D-V_GS curve) can be explained well by introducing positive fixed charges and defect states in the back interface region. It was found that the positive fixed charge and the defect density of a-Si:H TFT with an organic passivation layer are higher than those of conventional a-Si:H TFT with a silicon-nitride (SiN_x) passivation layer. The simulation shows that the front and back interfaces interact and this explains why the passivation affects the device performance such as V_th and S-factor in a-Si:H TFTs