4-µm LSI on SOS using coplanar-II process

SOS Si-gate 4-µm NMOS devices using a coplanar process (Coplanar-II process) have been investigated for the purpose of improving thé power-delay product and SOS LSI reliability. The gate breakdown field is improved by more than a factor of two (8.7 MV/cm) over that of transistors fabricated by a conventional SOS process. Two types of anomalous drain leakage currents which flow along the edge of the silicon island formed by using the conventional SOS process are suppressed. A typical drain leakage current is7 times 10^{-11}A/8 µm. The typical values of speed and power-delay product are 0.70 ns and 0.21 pJ for 4-µm channel length devices and 0.57 ns and 0.17 pJ for 3-µm devices. These values are 1.6 times faster than that of MOS/bulk due to a lack of stray capacitance in MOS/SOS. The temperature dependence of the delay time in NMOS/SOS E/D devices can be minimized by choosing the load transistor threshold voltage (VTD) to be -2.1 V. This is attributed to the higher temperature dependence of VTDthan that of MOS/bulk. The Coplanar-II process with Si-gate 4-µm NMOS/SOS is successfully applied to the fabrication of a 1300-gate LSI, RF0 (Register File 0). The circuitry has a unique register port which can be addressed from two independent ports simultaneously. In order to obtain higher speed and lower power, four kinds of threshold voltages are used. The circuits give rise to stable operation without any timing pulse such as a precharge and a higher internal access time of 25 ns in RF0, which consists of 256-bit memory and peripheral control circuit.     

Velocity saturation effect on short-channel MOS transistor capacitance

To analyze short-channel effects of MOS transistor ac characteristics, a two-dimensional device simulator has been used to extract MOS transistor capacitances. The results of simulation and measurements agree quite well. Several causes of short-channel effects are explained by the simulations. Velocity saturation effects are found to play a key role in the gradual increase in Cgd. Also holes in the accumulation region and the two-dimensional effect or the influence of the back-gate field from the drain are important in explaining the short-channel effect of MOS transistor capacitance.     

A JMOS transistor fabricated with 100-Å low-pressure nitrided-oxide gate dielectric

A Junction MOS (JMOS) transistor is proposed to offer increased performance over conventionally scaled NMOS devices as the gate dielectric thickness is reduced. The design, fabrication, and characterization of the JMOS device with a 100-Å gate dielectric is presented. Conventionally scaled NMOS and JMOS devices with gate lengths down to 1 µm are compared. The JMOS devices show a 25- percent increase in channel electron mobility and a 15-percent increase in drain current for equivalent gate drives with minimal adverse short-channel effects.     

A simple approach for accurately modeling the threshold voltage of short-channel mosts

We present a theory which models short-channel effects in MOS transistors (MOST). Our approach accounts for the effects of the source and drain depletion regions on the energy band configuration and the effective depletion layer charge under the channel. We derive an equation for low drain bias threshold voltage which accurately predicts the measured threshold on devices ranging in size from very small (1.5 μm) to very large (100 μm) effective channel lengths. The equation reliably predicts the phenomenon of decreasing threshold voltage and body effect observed experimentally from devices of decreasing channel length. The equation is valid for any bulk silicon MOS technology provided that the substrate doping is approximately uniform (i.e. ion-implantation has not been used to adjust the threshold). Our approach can be applied directly to the modeling of the short-channel drain to source current. This application of the theory will be presented in a later paper.     

Analysis of high-frequency thermal noise of enhancement mode MOS field-effect transistors

The high-frequency thermal noise in the drain and the gate of an enhancement mode MOS field-effect transistor was analyzed by using the transmission line model of the channel. The analysis gave the mean squared noise current generators of the drain and the gate and their correlation. The correlation coefficient of the drain and the gate noise was zero for zero drain voltage and was 0.395j at saturation. The noise figure of the MOS field-effect transistor was calculated from the result of the analysis. The high-frequency noise characteristics of an MOS field-effect transistor were similar to those of a junction gate field-effect transistor.     

Effects of gate notching profile defect on performance characteristics of short-channel NMOSFET with channel length of 0.12 /spl mu/m

In this letter, we report the effects of gate notching on the performance characteristics of short-channel NMOS transistor with the gate oxide thickness of 32 /spl Aring/. The significant gate-notching defect into channel region brings about the serious degradation of such transistor performances as transconductance (G/sub m/) characteristic and subthreshold swing (S/sub t/), resulting in increases of threshold voltage (V/sub TH/) and leakage current (I/sub OFF/) and the considerable reduction of drive current (I/sub ON/). We will suggest the local thickening of gate oxide as a main mechanism of its effects and show that lack of gate-to-source/drain extension (SDE) overlap may be an additional reason for the degradation of I/sub ON/ with increasing the notch depth.     

Punching through device and its integration—Static induction transistor

Static induction transistor (SIT) having a short-channel structure is characterized by small gate capacitance, high transconductance, and nonsaturation current-voltage characteristic. The major mechanism of current transport in SIT is majority-carrier injection due to barrier height control at the intrinsic gate in the channel. When the channel is completely pinched off due to the gate-to-channel built-in voltage in a junction-gate SIT (JSIT), there appears a normally-off SIT. In the forward gate bias operation of JSIT, which is called bipolar mode SIT (BSIT), the switching speed is far more improved from the conventional JSIT. BSIT exhibits saturation current-voltage characteristic. In BSIT, the drain voltage for the onset of current saturation is lower than that of the bipolar transistor and the current density is very high, leading to characteristics of low impedance, high transconductance, and high current gain. Applications of SIT in LSI are discussed especially concentrating on the BSIT. SIT logic circuit (SITL) containing BSIT exhibits short propagation delay time and low power dissipation and is very promising in the future development of VLSI.     

High-voltage SOS/MOS devices and circuit elements: Design, fabrication, and performance

High-voltage metal-oxide-semiconductor (HVMOS) transistors fabricated with low-voltage MOS circuits on the same silicon-on-sapphire (SOS) chip are critical for EAROM's and plasma display applications. An examination of the voltage limitations in conventional MOS is described. Several approaches to fabricating HVMOS transistors are analyzed, including the MOS tetrode, the extended drain MOST, and the double diffused MOST. Results of parameter tests on these devices are given and characteristics of HVMOS circuit elements discussed.     

A high-speed logic LSI using diffusion self-aligned enhancement depletion MOS IC

This paper reports the design, fabrication, and characterization of a diffusion self-aligned enhancement depletion (DSA-ED) MOS IC. It is shown that using DSA structure, a short channel MOST with effective submicron channel length can be realized even by standard photolithographic techniques. High-speed characteristics of a DSA MOST, high gain factors, and small drain junction capacitance are described. The advantage of an ED configuration is discussed. To evaluate the basic performance of the gate, 19-stage ring oscillators with various device sizes have been developed. In the ring oscillator design, the high gain factors of the DSA MOST are fully utilized to minimize the device size and upgrade the performance and packing density. A propagation delay time of 0.65 ns, a power dissipation of 0.15 mW, a power delay product of 0.10 pJ at the supply voltage 2 V, and a packing density of 510 gate/mm/SUP 2/ have been obtained by the single-level metal interconnections of 7 /spl mu/m details. A 4-bit arithmetic logic unit (ALU) has been developed with the same design principle and device size to obtain the 2.9 ns/gate, 0.71 mW/gate performance at the supply voltage of 5 V and 141 gates/mm/SUP 2/ packing density.     

On the short-channel theory for MOS transistor

An attempt is made to derive rigorous analysis for the short-channel MOS transistor on the basis of the 2-D Poisson's equation. The analysis is able to predict a correct dependence of the threshold voltage on channel length and drain voltage, avoids the need for the definition of an average depletion charge density, and gives more physical insight into the short-channel effects     

Design and fabrication of 50-nm thin-body p-MOSFETs with a SiGeheterostructure channel

Thin-body p-channel MOS transistors with a SiGe/Si heterostructure channel were fabricated on silicon-on-insulator (SOI) substrates. A novel lateral solid-phase epitaxy process was employed to form the thin-body for the suppression of short-channel effects. A selective silicon implant that breaks up the interfacial oxide was shown to facilitate unilateral crystallization to form a single crystalline channel. Negligible threshold voltage roll-off was observed down to a gate length of 50 nm. The incorporation of Si_0.7Ge_0.3 in the channel resulted in a 70% enhancement in the drive current. This is the smallest SiGe heterostructure-channel MOS transistor reported to date. This is also the first demonstration of a thin-body MOS transistor incorporating a SiGe heterostructure channel     

Closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted SOI NMOS devices with lightly-doped drain structure biased in strong inversion

This paper reports a closed-form analytical drain current model considering energy transport and self-heating for short-channel fully-depleted (FD) SOI NMOS devices with lightly-doped drain (LDD) structure. As verified by the two-dimensional (2-D) simulation results, the analytical drain current model considering energy transport and self-heating provides an accurate prediction of the drain current behavior of the 0.25-/spl mu/m FD SOI NMOS device with and without an LDD structure. From the analytical model, with the LDD structure, the device has a smaller effective electron mobility at a low drain voltage, where lattice temperature is dominant, and a higher effective mobility at a high drain voltage, where electron temperature dominates, as compared to the non-LDD device.     

The effect of LAC doping on deep submicrometer transistor capacitances and its influence on device RF performance

In this paper, we have systematically investigated the effect of lateral asymmetric doping on the MOS transistor capacitances and compared their values with conventional (CON) MOSFETs. Our results show that, in lateral asymmetric channel (LAC) MOSFETs, there is nearly a 10% total gate capacitance reduction in the saturation region at the 100-nm technology node. We also show that this reduction in the gate capacitance contributes toward improvement in f/sub T/, f/sub max/, and RF current gain, along with an improved transconductance in these devices. Our results also show that reduced short-channel effects in LAC devices improve the RF power gain. Finally, we report that the lateral asymmetric channel doping gives rise to a lower drain voltage noise spectral density compared to CON devices, due to the more uniform electric field and electron velocity distributions in the channel.     

Ion-implanted complementary MOS transistors in low-voltage circuits

Simple but reasonably accurate equations are derived which describe MOS transistor operation in the weak inversion region near turn-on. These equations are used to find the transfer characteristics of complementary MOS inverters. The smallest supply voltage at which these circuits will function is approximately 8kT/q. A boron ion implantation is used for adjusting MOST turn-on voltage for low-voltage circuits.     

A new self-aligning poly-contact technology for MOS LSI

A new self-aligning contact technology suitable for high density MOS LSI is proposed. This technology includes the following steps: 1) coating the polysilicon gate and interconnection areas by the photosensitive resist and baking it into polymalization. With an appropriate viscosity, resist thickness becomes thinner only above the polysilicon areas; and 2) removing selectively the thinned parts of the resist above the polysilicon areas using photo engraved openings of newly coated resist as a mask. This technology is applicable to the conventional Si-gate MOS processes and especially useful for short-channel MOSFET devices because it does not require a high temperature treatment that greatly spreads out the implanted doses compared with the conventional self-aligning contact technology. The high potential of this technology for MOS LSI is verified by the good yield and the high performance of the CMOS PLL (phase-locked-loop) LSI.     

Double ion implanted V-MOS technology

An n-channel double ion implanted (or diffused] lateral V-MOS structure (D-V-MOS) for LSI digital application is presented. The effective channel is formed by the vertical difference in an n-type and a p-type impurity profile on a high resistive p-type substrate through a V-groove technique. Thus the threshold voltage and effective channel length of the D-V-MOS can be directly and accurately controlled by ion implantation. Very short-channel length (0.1 to 0.2 /spl mu/m) MOS devices with good electrical characteristics can thus be realized. A simple fabrication process with 5 masking steps for an n-channel self-isolated self-aligned enhancement/depletion (E/D) D-V-MOST device is presented. The fabrication procedures are described. Special features associated with the V structure are discussed. The short-channel effect is treated. It is found that the substrate sensitivity due to source-substrate biasing for a short-channel D-V-MOS is reduced significantly, even with a 1000-/spl Aring/ gate oxide thickness.     

Parasitic bipolar effects in submicrometer GaAs MESFET's

We report the observation for the first time of parasitic bipolar action in GaAs MESFET's. It manifests itself in the form of increased transconductance at higher drain voltage, abrupt change in output conductance (kink effect) around 4-V drain-source voltage, and a gate-voltage-dependent substrate current. These effects are explained by electron-hole pair generation in the high-field region at the drain. The holes generated are injected into the substrate where they form the base region of a parasitic lateral bipolar transistor. The effect also explains a new breakdown mechanism for short-channel enhancement-mode MESFET's.     

Measurement of MOS current mismatch in the weak inversion region

Measures the current matching properties of MOS transistors operated in the weak inversion region. The authors measured a total of about 1400 PMOS and NMOS transistors produced in four different processes and report the results in terms of mismatch dependance on current density, device dimensions, and substrate voltage, without using any specific model for the transistor     

A one-dimensional theory on the effects of diffusion current and carrier velocity saturation on E-type IGFET current-voltage characteristics

Current-voltage characteristics of an enhancement-type insulated gate field-effect transistor (E-type IGFET) are analyzed based on a one-dimensional model, taking account also of the diffusion current component. Explicit formulae for the entire I-V characteristic curve are given. The solution for the triode characteristic shows considerable deviation from “drift current theory” in terms of turn-on voltage (or threshold voltage) and drain voltage at just saturation. The solution for the pentode characteristic taking account of carrier's saturation velocity, shows that the increase in drain current per unit drain voltage is larger in short-channel devices than in long-channel devices. Agreement with experiment is very good.     

Analytical I-V relationship incorporating field-dependent mobility for a symmetrical DG MOSFET with an undoped body

A simple expression explicitly relating the surface potential to the surface electric field of a symmetrical double-gate (DG) MOS capacitor is proposed. The expression does not contain the floating-body potential as an implicit variable. It is used to derive, assuming the validity of the gradual-channel approximation, an analytical model expression for the current-voltage relationship of a DG MOS field-effect transistor. The effects of mobility degradation at high vertical electric field and velocity saturation at high lateral electric field are incorporated. The model expression is continuously valid from the subthreshold to the quasi-linear regimes of operation and up to a well-defined drain saturation voltage. Beyond this saturation voltage, the gradual-channel approximation breaks down within a region near the drain end of the channel. The electric-field distribution within this region is estimated by solving a two-dimensional Poisson's equation. Further implications of the model are derived by simplifying the expression in different regimes of operation using various approximations.