用于IEEE802．11b／g WLAN直接下变频接收机的射频前端设计

介绍了一种应用于IEEE802．11b／g无线局域网接收机射频前端的设计。基于直接下变频的系统架构。接收机集成了低噪声放大器、I／Q下变频器、去直流偏移滤波器、基带放大器和信道选择滤波器。电路采用TSMC0．18μm CMOS工艺设计,工作在2．4GHz ISM（工业、科学和医疗）频段,实现的低噪声放大器噪声系数为0．84dB,增益为16dB,S11低于-15dB,功耗为13mW;I／Q下变频器电压增益为2dB,输入1dB压缩点为-1 dBm,噪声系数为13dB,功耗低于10mw。整个接收机射频前端仿真得到的噪声系数为3．5dB,IIP3为-8dBm,IP2大于30dBm,电压增益为31dB,功耗为32mW。     

A 240-MHz Low-Pass Filter With Variable Gain in 65-nm CMOS for a UWB Radio Receiver

An integrated fifth-order continuous-time low-pass filter for a WiMedia ultrawideband radio receiver is described in this paper. The prototype filter is realized with a passive pole at the filter input and a fourth-order leapfrog filter in which the gm-C technique with pseudodifferential transconductors is used. The transconductors do not include internal nodes, and they are designed to have a nominal 26-dB dc gain, of which process, voltage, and temperature variations are controlled by means of a negative resistance circuit. The losses of the low-dc-gain filter integrators are already taken into account in the filter synthesis. The passband edge frequency of the implemented filter is 240 MHz in order to receive multiband-orthogonal-frequency-division-multiplexing signals using the direct-conversion topology. The voltage gain of the filter can be controlled from 9 to 43 dB in the 1-dB gain steps. The filter achieves a 7.8-$hbox{nV}surdhbox{Hz}$ input-referred noise density, a $-$8-dBV out-of-band third-order intermodulation intercept point, and a $+$ 15-dBV out-of-band second-order intermodulation intercept point. The circuit uses a 1.2-V supply and has been fabricated in a modern 65-nm CMOS technology.      

A 60-GHz Phased Array Receiver Front-End in 0.13-$mu {hbox{m}}$ CMOS Technology

This paper presents a fully integrated dual-antenna phased-array RF front-end receiver architecture for 60-GHz broadband wireless applications. It contains two differential receiver chains, each receiver path consists of an on-chip balun, ag_m-boosted current-reuse low-noise amplifier (LNA), a sub-harmonic dual-gate down-conversion mixer, an IF mixer, and a baseband gain stage. An active all-pass filter is employed to adjust the phase shift of each LO signal. Associated with the proposed dual conversion topology, the phase shift of the LO signal can be scaled to one-third. Differential circuitry is adopted to achieve good common-mode rejection. The g_m-boosted current-reuse differential LNA mitigates the noise, gain, robustness, stability, and integration challenges. The sub-harmonic dual-gate down-conversion mixer prevents the third harmonic issue in LO as well. Realized in a 0.13-mum 1P8M RF CMOS technology, the chip occupies an active area of 1.1 times 1.2 mm². The measured conversion gain and input P1 dB of the single receiver path are 30 dB and -27 dBm , respectively. The measured noise figure at 100 MHz baseband output is around 10 dB. The measured phased array in the receiver achieves a total gain of 34.5 dB and theoretically improves the receiver SNR by 4.5 dB. The proposed 60 GHz receiver dissipates 44 mW from a 1.2 V supply voltage. The whole two-channel receiver, including the vector modulator circuits for built-in testing, consumes 93 mW from a 1.2 V supply voltage.     

Design of a High Performance 2-GHz Direct-Conversion Front-End With a Single-Ended RF Input in 0.13 $mu$m CMOS

A 2.1 GHz CMOS front-end with a single-ended low-noise amplifier (LNA) and a double balanced, current-driven passive mixer is presented. The LNA drives an on-chip transformer load that performs single-ended to differential conversion. A detailed comparison in gain, noise, and second and third order linearity performance is presented to motivate the choice of a current-driven passive mixer over an active mixer. The front-end prototype was implemented on a 0.13 $mu$m CMOS process and occupies an active chip area of 1.1 mm $^{2}$. It achieves 30 dB conversion gain, a low noise figure of 3.1 dB (integrated from 40 KHz to 1.92 MHz), an in-band IIP3 of ${-}$12 dBm, and IIP2 better than 39 dBm, while consuming only 12 mW from a 1.5 V power supply.      

A 2.4 GHz CMOS Low-IF Receiver Front-End for WLAN Applications

A CMOS low-IF receiver front-end applied for Wireless Local Area Networks (WLANs) is presented in this paper. The receiver front-end comprises a low noise amplifier (LNA), a down-converter, a single-to-fully converter, a polyphase filter, and a summator/subtractor. This low-IF architecture achieves 0.46° phase error and 0.7 dB gain mismatch in I–Q channels while the 2.4 GHz RF signal is down-converted into 100 MHz of IF band. The cascaded noise figure (NF) of LNA and polyphase network is 4.89 dB within the WLANs' requirement. The chip realized in a 0.6 m CMOS technology occupys 2.4 mm × 2.1 mm active area. From a single 3.3 V power supply, it consumes 300 mW power.     

A New Transceiver Architecture for the 60-GHz Band

A new “half-RF” architecture incorporates a polyphase filter in the signal path to allow the use of a local oscillator frequency equal to half the input frequency. The receiver performs 90 $^{circ}$ phase shift and two downconversion steps to produce quadrature baseband outputs. The transmitter upconverts the quadrature baseband signals in two steps, applies the results to a polyphase filter, and sums its outputs. Each path employs a dedicated 30-GHz oscillator and is fabricated in 90-nm CMOS technology. The receiver achieves a noise figure of 5.7–7.1 dB and gain/phase mismatch of 1.1 dB/2.1$^{circ}$ while consuming 36 mW. The transmitter produces a maximum output level of $-$7.2 dBm and an image rejection of 20 dB while drawing 78 mW.      

A Short Range, Low Data Rate, 7.2 GHz-7.7 GHz FM-UWB Receiver Front-End

A 9 mW FM-UWB receiver front-end for low data rate ( $≪$$ hbox{50~kbps}$), short range ( $≪$$hbox{10~m}$) applications operating in the ultra-wideband (UWB) band centered at 7.45 GHz is described in this paper. A single-ended-to-differential preamplifier with 30 dB voltage gain, a 1 GHz bandwidth FM demodulator, and a combined (preamp/demodulator) receiver front-end were fabricated in 0.25 $muhbox{m}$ SiGe:C BiCMOS and characterized. Measured receiver sensitivity is $-hbox{85.8~dBm}$ while consuming 9 mW from a 1.8 V supply, and $-hbox{83~dBm}$ consuming 6 mW at 1.5 V. 15-20 m range line-of-sight in an indoor environment is realized, justifying FM-UWB as a robust radio technology for short range, low data rate applications. Multi-user and interference capabilities are also evaluated.      

3-D Integration of 10-GHz Filter and CMOS Receiver Front-End

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mum CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.     

A Fully Integrated Variable-Gain Multi-tanh Low-Noise Amplifier for Tunable FM Radio Receiver Front-End

In this paper, we present a two-stage variable-gain low-noise amplifier (LNA) used in a frequency modulation (FM) radio receiver front-end for a variety of portable audio devices. We also describe a tunable antenna interface and a voltage regulator used in the front-end. The front-end can be tuned to resonate at FM frequencies from 63 to 129 MHz. The two-stage LNA achieves a programmable small-signal voltage gain from 0.5 to 32.5 dB in around 1-dB steps across the FM band from 76 to 108 MHz. Its input-referred noise voltage is less than 1.5 ${hbox {nV}}/sqrt{hbox {Hz}}$ in the high gain mode. Furthermore, the linearity of the LNA and front-end is improved by employing the multi-tanh design principle. In the low and high gain modes of the LNA, the measured IIP3 are $-$5.2 and $-$ 16.5 dBm, respectively, compared with $-$10.5 and $-$ 25.5 dBm without using the multi-tanh doublets. The whole LNA is fabricated in a TSMC 0.18-$mu{hbox {m}}$ CMOS technology. It draws maximum 4.5 mA current (5.5 mA including the regulator) from a 1.35-V supply and occupies 0.15 ${hbox {mm}}^{2}$ of chip area. Experimental and simulation results are both provided to demonstrate the performance of the LNA and front-end.      

A 22–29-GHz UWB Pulse-Radar Receiver Front-End in 0.18-$mu{hbox{m}}$ CMOS

The design of a CMOS 22–29-GHz pulse-radar receiver (RX) front-end for ultra-wideband automotive radar sensors is presented. The chip includes a low-noise amplifier, in-phase/quadrature mixers, a quadrature voltage-controlled oscillator (QVCO), pulse formers, and baseband variable-gain amplifiers. Fabricated in a 0.18-$mu{hbox{m}}$ CMOS process, the RX front-end chip occupies a die area of 3 ${hbox{mm}}^{2}$. On-wafer measurements show a conversion gain of 35–38.1 dB, a noise figure of 5.5–7.4 dB, and an input return loss less than $-$14.5 dB in the 22–29-GHz automotive radar band. The phase noise of the constituent QVCO is $-$107 dBc/Hz at 1-MHz offset from a center frequency of 26.5 GHz. The total dc power dissipation of the RX including output buffers is 131 mW.      

A Fully Integrated 5 GHz Low-Voltage LNA Using Forward Body Bias Technology

A fully integrated 5 GHz low-voltage and low-power low noise amplifier (LNA) using forward body bias technology, implemented through a 0.18 $mu{rm m}$ RF CMOS technology, is demonstrated. By employing the current-reused and forward body bias technique, the proposed LNA can operate at a reduced supply voltage and power consumption. The proposed LNA delivers a power gain (S21) of 10.23 dB with a noise figure of 4.1 dB at 5 GHz, while consuming only 0.8 mW dc power with a low supply voltage of 0.6 V. The power consumption figure of merit $(FOM_{1})$ and the tuning-range figure of merit $(FOM_{2})$ are optimal at 12.79 dB/mW and 2.6 ${rm mW}^{-1}$, respectively. The chip area is 0.89 $,times,$0.89 ${rm mm}^{2}$.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

A Low Voltage Mixer With Improved Noise Figure

A 5.2 GHz low voltage mixer with improved noise figure using TSMC 0.18 $mu$m CMOS technology is presented in this letter. This mixer utilizes current reuse and ac-coupled folded switching to achieve low supply voltage. The noise figure of the mixer is strongly influenced by flicker noise. A resonating inductor is implemented for tuning out the parasitic components, which not only can improve noise figure but also enhance conversion gain. A low voltage mixer without resonating technique has also been fabricated and measured for comparison. Simulated results reveal that flicker corner frequency is lowered. The measured results show 4.5 dB conversion gain enhancement and 4 dB reduction of noise figure. The down-conversion mixer with resonating inductor achieves 5.8 dB conversion gain, ${-}16$ dBm ${rm P}_{{rm 1dB}},$ ${-}6$ dBm ${rm IIP}_{3}$ at power consumption of 3.8 mW and 1 V supply voltage.      

A Low-Noise and Low-Power Frequency Synthesizer Using Offset Phase-Locked Loop in 0.13-$mu{rm m}$ CMOS

In this letter, a fractional-N frequency synthesizer based on an offset phase-locked loop (OPLL) architecture is presented. The proposed synthesizer achieves low-noise as the two low-pass filters that are inherent in the OPLL highly suppresses the quantization noise from the delta-sigma modulator. In addition, it consumes low power by employing charge-recycling technique in the sub-PLL. A prototype synthesizer implemented in 0.13 $mu{rm m}$ CMOS process achieves 9 dB of noise reduction compared to a conventional PLL while consuming 3.2 mW of power.      

A Novel 3–5 GHz Active Matched Filter for Impulse Radio Ultra-Wideband

In this letter, a novel active matched filter for UWB-IR lower band (3.1–4.85 GHz) is presented. The signal to noise ratio is improved at the output using a tapped delay line with a common source amplifier. An artificial transmission line is used for wideband impedance matching. The matched filter achieves a power gain of 9.8 dB at center frequency. Input matching is better than ${-}19$ dB and output matching is better than ${-}15$ dB. The averaged SNR improvement is 4.6 dB using peak detection. Input referred 1-dB compression point is 0.7 dBm at the center frequency. The matched filter is biased from a 1.5 V supply with a total power consumption of 38 mW.      

A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband

A 250 MHz analog baseband chain for Ultra-Wideband was implemented in a 1.2 V 0.13 $mu$ m CMOS process. The chip has an active area of 0.8 mm $^{2}$. In the analog baseband, PGAs and filters are carried out by current-mode amplifiers to achieve wide bandwidth and wide dynamic range of gain, as well as low noise and high linearity. Besides, a current-mode Sallen–Key low-pass filter is adopted for effective rejection of out-of-band interferers. A 6th-order Chebyshev low-pass filter realized in ${rm G}_{rm m}$ -C topology is designed in the baseband chain for channel selection. Digitally-assisted DC-offset calibration improves second-order distortion of the entire chain. The design achieves a maximum gain of 73 dB and a dynamic range of 82 dB. Measured noise figure is 14 dB, an IIP3 of ${-}$6 dBV, and IIP2 of ${-}$5 dBV at the maximum gain mode. The analog baseband chain consumes 56.4 mA under supply of 1.2 V.      

A 1.2-V RF front-end with on-chip VCO for PCS 1900 direct conversion receiver in 0.13-/spl mu/m CMOS

In this paper, a 1.2-V RF front-end realized for the personal communications services (PCS) direct conversion receiver is presented. The RF front-end comprises a low-noise amplifier (LNA), quadrature mixers, and active RC low-pass filters with gain control. Quadrature local oscillator (LO) signals are generated on chip by a double-frequency voltage-controlled oscillator (VCO) and frequency divider. A current-mode interface between the downconversion mixer output and analog baseband input together with a dynamic matching technique simultaneously improves the mixer linearity, allows the reduction of flicker noise due to the mixer switches, and minimizes the noise contribution of the analog baseband. The dynamic matching technique is employed to suppress the flicker noise of the common-mode feedback (CMFB) circuit utilized at the mixer output, which otherwise would dominate the low-frequency noise of the mixer. Various low-voltage circuit techniques are employed to enhance both the mixer second- and third-order linearity, and to lower the flicker noise. The RF front-end is fabricated in a 0.13-/spl mu/m CMOS process utilizing only standard process options. The RF front-end achieves a voltage gain of 50 dB, noise figure of 3.9 dB when integrated from 100 Hz to 135 kHz, IIP3 of -9 dBm, and at least IIP2 of +30dBm without calibration. The 4-GHz VCO meets the PCS 1900 phase noise specifications and has a phase noise of -132dBc/Hz at 3-MHz offset.     

A novel low power flip-flop design using footless scheme

A highly compact source follower coupling based low-pass filter (LPF) topology is proposed that synthesizes a 3rd-order low-pass transfer function in a single stage with no use of operational amplifiers. Chopper stabilization technique is utilized to reduce 1/f noise for minimizing the in-band integrated noise. Implemented and simulated in a 0.18 μm CMOS process, the 3rd-order LPF achieves a ??3 dB bandwidth of 20 MHz with a 280 μA total current from a 1.4 V supply voltage, defining a power-per-pole/bandwidth efficiency of 6.5 μW/MHz. The output noise density at low frequencies is largely reduced with chopper stabilization technique. The integrated output noise from 10 kHz to 2 MHz is minimized from 22.47 to 7.04 μV_rms, with a 10.1 dB improvement. The averaged output noise density over the filter bandwidth is 9.4 nV/√Hz, which is mostly contributed by thermal noise of transistors.     

A Linearization Technique for RF Receiver Front-End Using Second-Order-Intermodulation Injection

A linearization technique is proposed in which low-frequency second-order-intermodulation $({rm IM}_{2})$ is generated and injected to suppress the third-order intermodulation $({rm IM}_{3})$. The proposed linearization technique is applied to both a low-noise amplifier (LNA) and a down-conversion mixer in an RF receiver front-end (RFE) working at 900 MHz. Fabricated in a 0.18$ mu{hbox{m}}$ CMOS process and operated at 1.5 V supply with a total current of 13.1 mA, the RFE delivers 22 dB gain with 5.3 dB noise figure (NF). The linearization technique achieves around 20 dB ${rm IM}_{3}$ suppression and improves the RFE's ${rm IIP}_{3}$ from $-$ 10.4 dBm to 0.2 dBm without gain reduction and noise penalty while requiring only an extra current of 0.1 mA.      

A Single-Ended Fully Integrated SiGe 77/79 GHz Receiver for Automotive Radar

A single-ended 77/79 GHz monolithic microwave integrated circuit (MMIC) receiver has been developed in SiGe HBT technology for frequency-modulated continuous-wave (FMCW) automotive radars. The single-ended receiver chip consists of the first reported SiGe 77/79 GHz single-ended cascode low noise amplifier (LNA), the improved single-ended RF double-balanced down-conversion 77/79 GHz micromixer, and the modified differential Colpitts 77/79 GHz voltage controlled oscillator (VCO). The LNA presents 20/21.7 dB gain and mixer has 13.4/7 dB gain at 77/79 GHz, and the VCO oscillates from 79 to 82 GHz before it is tuned by cutting the transmission line ladder, and it centres around 77 GHz with a tuning range of 3.8 GHz for the whole ambient temperature variation range from $- hbox{40},^{circ}{hbox{C}}$ to $+ hbox{125},^{circ}{hbox{C}}$ after we cut the lines by tungsten-carbide needles. Phase noise is $-$90 dBc/Hz@1 MHz offset. Differential output power delivered by the VCO is 5 dBm, which is an optimum level to drive the mixer. The receiver occupies 0.5 ${hbox{mm}}^{2}$ without pads and 1.26 ${hbox{mm}}^{2}$ with pads, and consumes 595 mW. The measurement of the whole receiver at 79 GHz shows 20–26 dB gain in the linear region with stable IF output signal. The input ${rm P}_{rm 1dB}$ of the receiver is $-$35 dBm.