N/P~+硅外延生长

我们采用 SiCl_4/H_2体系以 PCl_3作汽相掺杂剂,在水平反应器中对 n/p~+硅外延进行了研究。利用衬底背面迁移掩蔽和二步外延生长工艺,较好地抑制了来自重掺硼(0.5～1.5×10~(20)厘米~(-3))衬底的自掺杂效应。稳定地制备了厚度5～8微米、电阻率1～3欧姆·厘米、过渡层小于0.8微米、均匀性较好的 n 型外延层。生长的 n/p~+外延材料用于制作穿通二极管,外延 p-n 结特性好。已作出12千兆赫下输出34毫瓦的穿通二极管。     

P~+-n~+隧道结的比接触电阻

本文根据Kane的直接隧穿理论,结合欧姆接触的特点,导出了p~+-n~+隧道结比接触电阻的计算公式.此式适用于直接能隙半导体,也适用于Si.在N_D+5×10~(20)cm~(-3)的磷浓度下,对一系列N_A值,按此式计算了Al/n~+-Si的比接触电阻R_(co)结果与Finetti等的测量值在数量级上完全一致.证明AL/n~+-Si的R_c基本上由其中的p~+-n~+结决定,因而与合金工艺有密切关系.     

简讯

20千兆赫大功率砷化镓双漂移区IMPATT二极管日本日立公司中央研究室报导了大功频砷化镓双漂移区IMPATT二极管的研究结果。在一次加热过程中,在(100)晶向的掺硒衬底上用连续液相外延生长p~+,p和n型层,以形成p~+—p—n—n~+结构。n型层杂质为锡,p~+和P型层杂质为锗。n和p型外延层厚度小于2微米,其误差控制在0.25微米以内,表面平     

在薄硅外延片上制备高频肖特基势垒二极管

采用超高真空化学气相沉积技术,在n型重掺Si衬底上生长了轻掺的薄硅外延层,利用扩展电阻和原子力显微分析对外延层进行了检验.结果表明,重掺Si衬底与薄硅外延层之间的界面过渡区陡峭,外延层厚度在亚微米级,掺杂浓度为10 1 7cm- 3.在此外延片上制备了高频肖特基二极管的原型器件,与传统的硅基肖特基二极管相比截止频率有了大幅提高     

硅双层特高阻厚层的完美外延

采用四氯化硅氢还原法在钟罩立式高频加热外延炉内掺杂锑的硅衬底上制备了特高阻双层结构(n_2~-/n_1~-/n~+)外延片,n_2~-层电阻率～150Ω·cm,n_1~-层电阻率～50Ω·cm,外延层总厚度达60μm时仍不产生冠状边沿,结晶完美。用于制作BSIT,得到非常满意的结果。     

砷化镓气相掺硫外延和亚微米薄层的制备

本文介绍了Ga-AsCl_3-H_2体系,研究了气相外延时硫的掺杂行为,讨论了硫的掺杂机理和生长了亚微米薄层。制得的亚微米外延层的质量表明,表面形貌良好,缺陷少,重复性好。典型的电学性质为:当厚度≤0.4μm和浓度为1—2×10~(17)/cm~3时,击穿电压V_B=7—10V。在单层和多层外延结构中,界面浓度基本是突变的,过渡区约0.1μm。这些外延片已用于制备变容管和远红外探测器等。     

在薄硅外延片上制备高频肖特基势垒二极管

采用超高真空化学气相沉积技术,在n型重掺Si衬底上生长了轻掺的薄硅外延层,利用扩展电阻和原子力显微分析对外延层进行了检验.结果表明,重掺Si衬底与薄硅外延层之间的界面过渡区陡峭,外延层厚度在亚微米级,掺杂浓度为1017cm-3.在此外延片上制备了高频肖特基二极管的原型器件,与传统的硅基肖特基二极管相比截止频率有了大幅提高.     

Ga_(0.47)In_(0.53)As材料液相外延生长的组分控制研究

本文分析了Ga_(0.47)In(0.53)As材料生长中影响材料组分变化的因素,简要地给出了生长合适组分外延层的料源配制公式及其应用结果.采用适当的生长工艺可使外延层的横向组分平均偏离控制在±1.0%以内,纵向组分平均偏离在±1.4%以内,一源多炉生长的炉间外延层组分的平均偏离在±2%以内.分凝系数测量结果说明:三元层的生长主要是与组分的扩散密切有关,而与生长界面的动力学因素关系不太紧密.     

超薄层常压外延工艺研究

为了满足一种3 mm雪崩渡越二极管的技术要求,改进了常压外延工艺,在PE-2061S硅外延设备上,实现了100 mm硅片超薄外延层的生长.外延层厚度为0.45～0.55μm,外延层与衬底之间的过渡区宽度大于0.2μm.过渡区宽度以及外延层厚度和掺杂浓度的精确控制,提高了器件的微波性能.     

HgCdTe镶嵌阵列现状

1.液相外延材料用液相外延法在CdTe衬底上生长成器件品级的HgCdTe,其截止波长范围为3～14微米。这一工艺是前两年研究的。目前,液相外延层与块晶体材料相比,前者的截止波长一致性较高。在中波红外外延层上,生成态载流子浓度通常适用于制造二极管,而长波红外外延层则很易调节成适用的浓度。在混合式器件所需要的厚度范围内,生成态外延层的厚度可控制为变化不超过1微米。目前外延层的尺寸仅受到所能获得的大单晶衬底的限制。     

用于双栅FET的n~+-n-n~-GaAs多层外延生长

采用Ga/AsCl_3/H_2体系,用SnCl_4作掺杂剂,已生长了用于双栅FET的n~+-n-n~-多层外延材料.在一次外延生长中连续生长的n~+-n-n~-多层外延材料的外延层厚度和载流子浓度的均匀性良好.用该材料制作的双栅FET的微波特性也有明显改善.在2GHz和8GHz下,NF分别为0.9dB和2.8dB,相关增益G_a分别为15.5dB和18dB.     

Improved germanium avalanche photodiodes

New kinds of germanium avalanche photodiodes with n+-n-p and p+-n structures were devised for improved excess noise and high quantum efficiency performance. Multiplication noise, quantum efficiency, and pulse response were studied and compared with those of the conventional n+-p structure diode. Multiplication noise of the new type of diodes were measured in the wavelength range between 0.63 and 1.52 μm. The effective ionization coefficient ratio of the p+-n diode was lower than unity at a wavelength longer than 1.1 μm and 0.6-0.7 at 1.52 μm, and that of the n+-n-p diode was 0.6-0.7 in the whole sensitive wavelength region. Response times were evaluated by using a mode-locked Nd:YAG laser beam and a frequency bandwidth wider than 1 GHz was estimated. Receiving optical power levels were compared with each other using parameters measured in this study.     

基于CMOS工艺的横向多晶硅p^＋p^-n^＋结红外微测辐射热计

基于多晶硅p-n结正向压降的温度特性,应用标准CMOS工艺,结合体硅微机械加工技术,研制成功非制冷红外微测辐射热计.本文详细分析了横向多晶硅p+p-n+结的温度特性,给出了正向压降温度变化率的理论表达式和实验测量值;并描述了微测辐射热计的设计思路和制作工艺.实验结果表明在室温(284～253K)附近,横向多晶硅p+p-n+结正向压降的温度变化率为1.5mV/K;在3～5μm红外波段,微测辐射热计的电压响应率为5.7×103V/W,黑体探测率D*为1.2×108cm.Hz1/2.W-1.     

SiGeC异质结功率二极管通态特性研究

研究了一种大功率低功耗p+(SiGeC)-n--n+异质结二极管结构,分析了Ge、C含量对器件正向通态特性的影响。结果表明:与常规的Si p-i-n二极管相比,在正向电流密度不超过1000 A/cm2情况下,p+(SiGeC)-n--n+二极管的正向压降有明显的降低。当电流密度为10 A/cm2时,Si p-i-n二极管的压降为0.655 V,而SiGeC异质结二极管的压降只有0.525 V,大大降低了器件的通态功耗。在相同正向电流密度的条件下,SiGeC异质结二极管在n-区存储的载流子比Si二极管的减少了1个数量级以上,这导致前者的关断时间远小于后者。     

Numerical analysis of electric field inside mesa p+-n-n+ avalanche diodes

Preliminary results of a numerical 2-dimensional analysis of the electric field and the space-charge region in silicon mesa p+-n-n+ diodes designed for avalanche transit-time operation are reported. It is shown that, for certain values of the bevel angles at the p+-n junction and the n-n+ interface, the electric field below the semiconductor surface exceeds the maximum field in the bulk material.     

外延层厚度对垂直结构6H-SiC光导开关特性影响的研究

设计了新颖的具有垂直结构的6H-SiC光导开关。首先采用离子注入工艺在半绝缘6H-SiC衬底两侧生成一层p+离子注入层,然后利用外延工艺在其中的一侧生长一层n+外延层,并将此侧定义为开关的阴极。利用二维半导体器件仿真软件,研究了n+外延层厚度对6H-SiC光导开关特性的影响。结果表明,增加外延层厚度可以提高开关的击穿电压;而开关的导通电流,首先随着n+外延层厚度的增加而减小,在n+外延层厚度为5?m达到最小值,随后随着厚度的增加,导通电流增加。     

Ultrafast GaAs microwave PIN diode

This letter describes what is believed to be the first successful realisation of GaAs PIN diodes. The vertical structure was grown on an n+ substrate by MOCVD of a 2 ?m, 1015 cm?3 unintentionally doped n? layer followed by a 0.3 ?m, 4×1019 cm?3 Zn doped p+ layer. The isolation and insertion loss of a single shunt-mounted device are typically ?27 dB and 0.7 dB, respectively. The switching speed of the device was measured to be less than 1 ns.     

A high threshold voltage uniformity MIS-like heterostructure FET using n+-Ge as a gate electrode

A new n+-Ge/ undoped-AlxGa1-xAs/ undoped-GaAs MISlike heterostructure FET (n+-Ge-HFET), using n+-Ge layer as a gate electrode material, is shown to have a high threshold voltage uniformity (sigmaV_{TH} = 11mV) over a large sample area of a 2-in wafer quadrant. This is thought to come from the FET structure, for which the threshold voltage is principally determined by the difference in the electron affinities of Ge and GaAs. The high VTHuniformity, as well as the positive FET characteristics (g_{m} = 170mS/mm,V_{TH} = 0.25V), makes n+-Ge-HFET very attractive for LSI application.     

Improved theory of ballistic transport in one dimension

Calculations are presented for the current/voltage characteristics of GaAs n+-n?-n+ ballistic diodes. The theory takes into account the thermal distribution of velocities with which electrons are injected from the n+ contacts. No unique power law behaviour is obtained suggesting that it is not possible to identify ballistic motion from measurements of current and voltage alone.     

Formation of TiN/TiSi2/p+-Si/n-Si by rapid thermal annealing (RTA) silicon implanted with boron through titanium

A low temperature method of fabricating conductive (3.5 Ω/ sq.) p⁺/n junction diodes possessing excellentI-Vcharacteristics with reverse-bias leakage less than -3 nA.cm^-2at -5 V is described. Single crystal n-type 〈100〉 Si is implanted with 60 keV¹¹B+through 0.028-µm thick sputtered Ti film. Rapid thermal annealing (RTA) in an N2ambient simultaneously forms a 0.36-µm deep p⁺/n junction and a 0.063-µm thick bilayer of TiN and TiSi2with a resistivity of 22 µΩ.cm. The electrical properties of these diodes are not degraded by annealing for 30 min at 500°C, suggesting that the outer layer of TiN is an effective diffusion barrier between TiSi2and Al.