点对多点服务的输入/输出排队ATM交换机性能分析

本文分析了一种具有点对多点服务能力的内部无阻塞输入／输出排队ATM交换机在反压控制下的性能指标。在每个输入端口信元的到达具有相同的强度，每个排头信元以一种相同的概率分布函数被复制成多个输往不同的输出端口的排头信元，复制后的排头柜元到达输出端口的概串相同为1/N，且输入、物出缓冲容量均为有限。为保证交换机内部不发生信元丢失，引入了反压机制（Backpressure）。本文利用矩阵几何分析法绘出了数值解，计算机仿真结果表明理论分析是正确的。     

基于逆向传输机制的反馈型两级交换结构

为解决FTSA-2-SS结构中的信元冲突、信元失序以及交换流程复杂化等问题,该文提出一种基于逆向传输机制的反馈型两级交换结构(FRTM-TSA)。该结构通过crossbar逆向传输机制使得任意输入端口均可获得其相邻端口的调度结果并以此对目标端口所反馈的缓存信息进行修正,基于修正后的信息进行算法调度使得FRTM-TSA能够避免信元冲突和信元失序,也无需在输出端口设置重排序缓存。理论分析和仿真结果均表明FRTM-TSA能够以相对简洁的交换结构和交换流程获得更优的时延性能。     

输入/输出ATM交换机在突发性业务下的性能

本文详尽分析了内部无阻塞输入／输出排队反压型ＡＴＭ交换机在突发性业务下信元丢失、交换机最大吞吐量等性能。输入端口信元的到达过程是ＯＮ－ＯＦＦ突发流，且ＯＮ态以概率ｐ发送信元，ＯＮ－ＯＦＦ长度为Ｐａｒｅｔｏ分布的随机变量；属于同一突发流的信元输往同一个输出端口，不同突发流的信元等概率输往不同的输出端口；输入／输出缓冲器长度有限，交换机加速因子Ｓ任意。本文同时比较了突发长度为周期／几何分布下的交换机性能，其结论对实际设计一输入／输出排队反压型ＡＴＭ交换机具有一定参考意义。     

具有纵横输入互连方式和缓冲结构的递归Knockout交换网络

本文提出了具有纵横输入（ＣｒｏｓｂａｒＩｎｐｕｔ）互连方式和输入缓冲（ＩｎｐｕｔＢｕｆｅｒｅｄ）结构的递归Ｋｎｏｃｋｏｕｔ交换网络（ＣＩＢＲＫＳ）．通过采用纵横输入互连方式可减少内部小交换单元的数目,并可使信元传送顺序不会受群输出端口数目的影响．而通过在每个输入端放置缓冲器可在保持丢失率性能不变的情况下,可使整个交换网络的级数减少,从而也就减少了信元在群网络中的传输时延．另外,在该结构中,通过把信元滤址的功能从每个小交换单元中提取出来放在每个输入端口,又进一步减少了小交换单元的功能．通过比较,我们认为,作为大规模ＡＴＭ交换网络结构,ＣＩＢＲＫＳ结构比传统的ＲＫＳ结构具有较好的性能／复杂度特性．     

一种新的高性能ATM共享存储交换单元

ATM交换单元中．可选用三种基本排队策略一输入捧队、输出捧队和共享存贮捧队。根据平均信元时延、吞吐量和信元丢失概率性能．最佳的排队策略是共享存储捧队。由于传统的共享存储交换单元必须缓冲经过交换单元的所有信元，因此交换单元的吞吐量和信元丢失概率性能仍不理想，特别是对于大规模交换单元情况更是如此。本文提出了一种新的高性能共享存储交换单元，称为阻塞信元共享存储（BCSM)交换单元。顾名思义，BCSM仅仅缓冲交换单元输入端口的阻塞信元，而不必缓冲经过交换单元的所有信元。均匀业务下的分析结果证明，BCSM交换单元比一般共享存贮交换单元具有更好的性能。     

均匀业务下反压型输入/输出排队ATM交换机的性能分析

本文利用矩阵几何分析法分析了内部无阻塞输入/输出排队反压型ATM交换机在均匀贝努利输入下的信元丢失、信元延时及吞吐量等性能指标。本文结论对实际设计一反压型输入/输出排队分组交换机具有一定参考意义。     

均匀业务下反压型输入／输出排队ATM交换机的性能分析

本文利用矩阵几何分析法分析了内部无阻塞输入／输出排队反压型ＡＴＭ交换机在均匀贝努利输出下的信元丢失、信元延时及吴吐量等性能指标。本文结论对实际设计一反压型输入／输出排队分组交换机具有一定参考意义。     

具有丢失优先级策略的输入／输出排队ATM交换机的性能分析

本文分析了一种输入排队缓冲器有丢失优先级的内部无阻塞输入／输出排队ＡＴＭ交换机在反压控制下的信元丢失指标。在每个输入端口高、低优先级信元的到达具有相同的强度，到达输出端口的概率相同为１Ｎ，且输入、输出缓冲容量均为有限。为保证交换机内部不发生信元丢失，引入了反压机制（Ｂａｃｋｐｒｅｓｓｕｒｅ）。文中表明，使用丢失优先级策略的交换机比纯输入／输出排队交换机更能满足不同业务服务等级ＱｏＳ（ＱｕａｌｉｔｙｏｆＳｅｒｖｉｃｅ）的丢失要求，而且所需缓冲容量减少。     

VOQ输出端解复用算法及其技术实现

目前的高速交换机大都采用虚拟输出排队(VOQ)方法,并把变长分组拆成定长信元后交换。已有的关于队列组织与管理的文章都着重于讨论N×N交换结构中每个端口对应于一个实际物理端口的情况,但在实际中经常需要对端口进行复用和解复用。我们针对863“实用化综合接入系统”边缘路由器子系统的设计特点,自行提出了基于输出子端口的队列组织与解复用算法。这篇文章阐述了该算法,并给出了算法的性能分析和具体实现。     

一种Tb/s量级带宽的光电混合路由交换系统的结构

提出一种采用光互连网络作为大容量路由器中的信息传输载体,以VCSEI/PIN作为光电、电光转换收发接口,用高速IC芯片来处理信息的光电混合太比特量级的大容量路由交换系统方案.通过采用高速分组交换芯片、可扩展的交换结构与共享储存排队方法,实现了交换机构规模可扩展到1024×1024,端口速率为2.5 Gb/s,信元丢失率小于l0-9的新型的光电混合路由交换核心模块.     

Structural Fault Testing of Embedded Cores Using Pipelining

The purpose of this paper is to develop a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a bypass mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested because they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the accessibility (of the core input and output ports) is solved as a shortest path problem. Finally, a pipelined test schedule is made to overlap accessing input ports (to send test patterns) and output ports (to observe the signatures). The experimental results show higher fault coverage and shorter test time.     

三维片上网络故障及拥塞感知的容错路由器设计

 三维片上网络中路由器的输入端口和交叉开关出现故障,将严重影响整个网络的性能,因此文章提出了一种故障及拥塞感知的容错路由器.通过增加一个冗余的输入端口和旁路总线,不仅能实现对输入端口和交叉开关容错的目的,而且还能在没有端口故障的情况下使用冗余端口有效地解决拥塞问题.实验表明此容错机制能够使得网络在故障路由器多、拥塞严重的情况下,仍然保持良好的性能.     

Non-blocking four-port optical router based on thermo- optic silicon microrings

By using silicon-on-insulator(SOI) platform, 12 channel waveguides, and four parallel-coupling one-microring resonator routing elements, a non-blocking four-port optical router is proposed. Structure design and optimization are performed on the routing elements at 1 550 nm. At drop state with a power consumption of 0 m W, the insertion loss of the drop port is less than 1.12 d B, and the crosstalk between the two output ports is less than-28 d B; at through state with a power consumption of 22 m W, the insertion loss of the through port is less than 0.45 d B, and the crosstalk between the two output ports is below-21 d B. Routing topology and function are demonstrated for the four-port optical router. The router can work at nine non-blocking routing states using the thermo-optic(TO) effect of silicon for tuning the resonance of each switching element. Detailed characterizations are presented, including output spectrum, insertion loss, and crosstalk. According to the analysis on all the data links of the router, the insertion loss is within the range of 0.13—3.36 d B, and the crosstalk is less than-19.46 d B. The router can meet the need of large-scale optical network-on-chip(ONo C).     

A load balancing bufferless deflection router for network-on-chip

The bufferless router emerges as an interesting option for cost-efficient in network-on-chip (NoC) design. However, the bufferless router only works well under low network load because deflection more easily occurs as the injection rate increases. In this paper, we propose a load balancing bufferless deflection router (LBBDR) for NoC that relieves the effect of deflection in bufferless NoC. The proposed LBBDR employs a balance toggle identifier in the source router to control the initial routing direction of X or Y for a flit in the network. Based on this mechanism, the flit is routed according to XY or YX routing in the network afterward. When two or more flits contend the same one desired output port a priority policy called nearer-first is used to address output ports allocation contention. Simulation results show that the proposed LBBDR yields an improvement of routing performance over the reported bufferless routing in the flit deflection rate, average packet latency and throughput by up to 13%, 10% and 6% respectively. The layout area and power consumption compared with the reported schemes are 12% and 7% less respectively.     

用于反熔丝FPGA的多标准IO接口电路

针对高可靠性领域和复杂环境对大规模反熔丝FPGA器件的迫切需求,设计了一种新的用于反熔丝FPGA的可动态配置IO接口电路。该IO接口电路具有宽的输入输出电压范围,能实现多驱动调节,支持一系列不同电平模式。通过对反熔丝单元进行编程配置,该IO接口电路可兼容多种IO标准,内核电压为2.5 V,端口电压可在3.3 V与5 V之间转换。仿真与测试结果表明,该IO接口电路满足设计要求,接口速度优于国外同类产品。     

衬底防反灌电路的设计

以采样电路为对象,采用CMOS工艺,利用耗尽型场效应管的弘,特性设计电路,达到输入电压低于输出电压时,防止输出端的高电位向衬底反灌电流的目的。本设计能够在全输入电压范围内直接检测,并且不需要外部偏置电流源。在3V～5V的输入电压范围内仿真,最功耗60μＷ,在1μs内输出所需要逻辑信号,输入电压回升时具备40mV（可调）的延迟。可以有效防止输出端高电位向衬底反灌以及输入电压不稳定引起的输出信号跳动。     

Chirping of the waveguide grating router for free-spectral-range mode selection in the multifrequency laser

Because the transmission through each input-output combination of a conventional waveguide grating router consists of a periodic sequence of equal-height passbands spaced by the router free spectral range, the absolute laser oscillation wavelength and single-passband oscillation can be difficult to control for all the channels in the multifrequency waveguide grating router laser. However, the router can be designed to have one dominant passband, with the neighboring passbands experiencing lower transmission coefficients for all the input output combinations by means of chirping of the waveguide grating. Such chirping is discussed theoretically and is demonstrated experimentally.     

基于AXI4-Stream总线的数字视频接口IP核设计

针对数字视频IP核间高速流数据传输,设计并实现了一种基于AXI4-Stream总线的数字视频接口IP核,对外部输入ITU601格式的数字视频信号,将其格式转化为符合AXI4-Stream总线协议的信号,并通过IP核的主端口输出到下一级IP核的从端口。采用Xilinx ISE Design Suite 14.6软件综合设计实现,结合ISE自带ISim软件完成功能仿真,通过实际硬件电路验证了设计的正确性及可行性。     

On the stability of input-queued switches with speed-up

We consider cell-based switch and router architectures whose internal switching matrix does not provide enough speed to avoid input buffering. These architectures require a scheduling algorithm to select at each slot a subset of input buffered cells which can be transferred toward output ports. We propose several classes of scheduling algorithms whose stability properties are studied using analytical techniques mainly based upon Lyapunov functions. Original stability conditions are also derived for scheduling algorithms that are being used today in high-performance switch and router architectures