A 10.7-MHz IF-to-baseband ΣΔ A/D conversion system forAM/FM radio receivers

ΣΔ modulation with integrated quadrature mixing is used for analog-to-digital (A/D) conversion-of a 10.7-MHz IF input signal in an AM/FM radio receiver. After near-zero IF mixing to a 165 kHz offset frequency, the I and Q signals are digitized by two fifth-order, 32 times oversampling continuous-time ΣΔ modulators. A prototype IC includes digital filters for decimation and the shift of the near-zero-IF to dc. The baseband output signal has maximum carrier-to-noise ratios of 94 dB in 9 kHz (AM) and 79 dB in 200 kHz (FM), with 97 and 82 dB dynamic range, respectively. The IM3 distance is 84 dB at full-scale A/D converter input signal. Including downconversion and decimation filtering, the IF A/D conversion system occupies 1.3 mm² in 0.25-μm standard digital CMOS. The ΣΔ modulators consume 8 mW from a 2.5-V supply voltage, and the digital filters consume 11 mW     

A 1.2 mW RDS receiver for portable applications

A 0.9 V 1.2 mA fully integrated radio data system (RDS) receiver for the 88-108 MHz FM broadcasting band is presented. Requiring only a few external components (matching network, VCO inductors, loop filter components), the receiver, which has been integrated in a standard digital 0.18 /spl mu/m CMOS technology, achieves a noise figure of 5 dB and a sensitivity of -86dBm. The circuit can be configured and the RDS data retrieved via an I/sup 2/C interface so that it can very simply be used as a peripheral in any portable application. A 250 kHz low-IF architecture has been devised to minimize the power dissipation of the baseband filters and FM demodulator. The frequency synthesizer consumes 250 /spl mu/A, the RF front-end 450 /spl mu/A while providing 40 dB of gain, the baseband filter and limiters 100 /spl mu/A, and the FM and BPSK analog demodulators 300 /spl mu/A. The chip area is 3.6 mm/sup 2/.     

A 35-mW 3.6-mm/sup 2/ fully integrated 0.18-/spl mu/m CMOS GPS radio

A single-chip CMOS Global Positioning System (GPS) radio has been integrated using only a couple of external passive components for the input matching network and one external reference for the synthesizer. The receiver downconverts the GPS L1 signal at 1575.42 MHz to an IF of 9.45 MHz. The complete front-end and frequency synthesizer section have been integrated: low noise amplifier, image rejection mixer, IF active filter, and the full phase-locked loop synthesizer, including voltage-controlled oscillator and loop filter. The front-end measured performances are 81-dB maximum gain, 5.3-dB noise figure, and >30-dB image rejection. The synthesizer features a phase noise of -95 dBc/Hz at 1-MHz offset and a total integrated phase noise of less than 7/spl deg/ rms in the 500-Hz-1.5-MHz band. The front-end and the synthesizer draw, respectively, 11 and 9 mA from a 1.8-V supply. The architecture of the front-end and synthesizer has been geared to high level of integration and reduction of silicon area at the lowest possible power consumption. Consequently, the one reported here is the smallest and most integrated CMOS GPS receiver reported so far.     

A 2-V CMOS 455-kHz FM/FSK demodulator using feedforward offsetcancellation limiting amplifier

This paper presents a low-voltage low-power IF 455-kHz signal processor that contains a three-stage limiting amplifier and an FM/FSK demodulator. The limiting amplifier uses an on-chip feedforward offset cancellation circuit. The FM/FSK demodulator employs a quadrature detector that is composed of an on-chip phase detector and an external tank phase shifter. The demodulation constant is 20 mV/kHz with masimum ±10-kHz frequency deviation. The IF signal processor that consumes 2.3 mW from a single 2-V power supply demonstrates a high sensitivity of -72 dBm. It occupies an active area of 0.2 mm² using 0.6-μm digital CMOS technology     

On the use of Nauta's transconductor in low-frequency CMOS gm-C bandpass filters

This paper discusses the use of a transconductor, first proposed by Nauta for high frequency applications, in low frequency CMOS g_m -C bandpass filters. The behavior of the transconductor is examined in detail, showing that the robust implementation of higher-order low-voltage filters is possible for center frequencies in the lower megahertz region. The experimental results are presented of the realization of two prototypes, a 0.6-μm CMOS 18th-order real bandpass filter and a 0.35-μm CMOS 7th-order complex (14th-order bandpass) filter, both with a center frequency of 3 MHz and a passband of 1 MHz. These filters comply with the specifications for the channel-select stage of the Bluetooth short-range radio receiver     

An image-rejecting mixer and vector filter with 55-dB imagerejection over process, temperature, and transistor mismatch

This paper describes an image-rejecting mixer and vector filter for use in radio systems with channel bandwidths in the range of 1 MHz. The circuit replaces the SAW filter and second downconverter commonly used in this style of radio. Because the output of the circuit is at an IF of 5 MHz, traditional demodulation methods including limiting and FM discrimination can still be used. The circuit is based on a quadrature mixer that guarantees good performance despite device mismatches and process variation. The circuit consumes 29 mA at 3.3 V,and achieves better than 55-dB image rejection despite device mismatches and process variation and is implemented in a single-poly triple metal 0.5 μm CMOS process with linear capacitor implants. The circuit is designed for input signals from 125 to 250 MHz. Input referred voltage noise is 900 μVrms. The in-band IP3 is 18 dBm. By changing an external reference frequency, the passband width of the filter can be varied from 3 to 0.5 MHz     

An IF-to-Baseband Σ∆ Modulator for AM/FM/IBOC Radio Receivers With a 118 dB Dynamic Range

A single-bit fifth-order complex continuous-time IF-to-baseband SigmaDelta modulator for AM/FM/IBOC receivers is presented. The input IF is 10.7 MHz and the sampling frequency is 41.7 MHz. The modulator achieves a dynamic range of 118dB in AM mode (3 kHz BW), 98dB in FM mode (200 kHz BW), and 86dB in IBOC mode (500 kHz BW). The modulator's high dynamic range enables the realization of an AM radio receiver without a VGA and without an AM channel-selection filter, thereby reducing system complexity and cost. The elimination of the VGA also improves the sensitivity and the overall noise figure of the receiver. The modulator's spurious free dynamic range is 88 dB in the bandwidth from 25 to 525 kHz. The IM2 distance is 92 dB, and the IM3 distance is 91 dB. The ADC was fabricated in a one-poly five-metal 0.18-mum CMOS process with an active area of 6.0mm². It consumes 210 mW from a 1.8-V supply     

A 10.7-MHz switched-capacitor bandpass filter

An experimental 10.7-MHz switched-capacitor bandpass filter is demonstrated that exhibits a 400-kHz bandwidth with a 42-MHz sampling rate. Basic design issues of such high-frequency filters are also addressed with emphasis on dynamic range and power constraints. A theoretical square relation between power and center frequency agrees well with experimental results. The sixth-order differential bandpass filter chip occupies 2 mm² using a 2.25-μm gate double-poly CMOS technology     

High-frequency CMOS continuous-time filters

Fully integrated, high-frequency continuous-time filters can be realized in MOS technology using a frequency-locking approach to stabilize the time constants. A simple, fully differential integrator, optimized for phase-error cancellation, forms the basic element; a complete filter consists of intercoupled integrators. The center frequency of the filter is locked to an external reference frequency by a phase-locked loop. A prototype sixth-order bandpass filter with a center frequency of 500 kHz dissipates 55 mW and occupies 4 mm/SUP 2/ in a 6-/spl mu/m CMOS technology.     

A 56 mW Continuous-Time Quadrature Cascaded Σ∆ Modulator With 77 dB DR in a Near Zero-IF 20 MHz Band

A quadrature cascaded modulator with continuous-time loop filters is presented for a digital multi-stream FM radio receiver. The ADC achieves a dynamic range of 77 dB and 20 MHz bandwidth centered on an intermediate frequency of 10.5 MHz and is sampling at 340 MHz. The cascaded modulator comprises programmable analog second-order quadrature filters and a digital quadrature noise cancellation filter. The 0.5 chip in 90 nm CMOS consumes 56 mW from a 1.2 V supply.     

Integrated selectivity for narrow-band FM IF systems

An 18th-order all-pole continuous-time bandpass filter for IF (intermediate frequency) filtering purposes has been designed and integrated in a 3-μm CMOS process. Implemented using nine fully balanced, transconductor-capacitor coupled resonators, the filter features a 20-kHz bandwidth at 200-kHz center frequency and 54-dB dynamic range (IM3<-40 dB) and consumes 300 μA from a single 4-V supply. With the use of conventional phase-locked loop techniques for automatic tuning, the accuracy of the filter response is comparable to that of ceramic filters. As expected, the fundamental limitations of such an active implementation compared to a passive realization are noise and distortion     

A 3.3-V CMOS 10.7-MHz sixth-order bandpass ΣΔ modulatorwith 74-dB dynamic range

A 3.3-V bandpass ΣΔ modulator for IF sampling at 10.7 MHz in digital radio applications has been developed. The modulator presents a sixth-order single-loop architecture and features a 74-dB dynamic range in a 2OO-kHz signal bandwidth (FM signal), while for a 9-kHz signal bandwidth (AM signal) the dynamic range is 88 dB. The modulator has been integrated in a standard 0.35-μm CMOS technology using switched-capacitor technique and consumes 76 mW from a single 3.3V supply     

Design considerations and implementation of a DSP-based car-radio IF Processor

This paper describes design considerations and the implementation of a software defined radio receiver encompassing intermediate frequency (IF) digitization. The proposed system-on-chip performs the demodulation of both AM and FM stereo signals, digitized at the IF by means of a high dynamic range sigma-delta bandpass A/D converter. The chosen architecture combines hardware and software functions, trading flexible programmability with area occupancy. The software includes also true blind equalization of the FM signals, resulting in the rejection of the neighbor channels and of any other interfering signal, even under severe multipath conditions. The described chip, realized in a 0.18-/spl mu/m CMOS technology, occupies an area of 15.2 mm/sup 2/ and is enclosed in a 64-pin package.     

A Dual‐Mode 2.4‐GHz CMOS Transceiver for High‐Rate Bluetooth Systems

This paper reports on our development of a dual‐mode transceiver for a CMOS high‐rate Bluetooth system‐on‐chip solution. The transceiver includes most of the radio building blocks such as an active complex filter, a Gaussian frequency shift keying (GFSK) demodulator, a variable gain amplifier (VGA), a dc offset cancellation circuit, a quadrature local oscillator (LO) generator, and an RF front‐end. It is designed for both the normal‐rate Bluetooth with an instantaneous bit rate of 1 Mb/s and the high‐rate Bluetooth of up to 12 Mb/s. The receiver employs a dualconversion combined with a baseband dual‐path architecture for resolving many problems such as flicker noise, dc offset, and power consumption of the dual‐mode system. The transceiver requires none of the external image‐rejection and intermediate frequency (IF) channel filters by using an LO of 1.6 GHz and the fifth order on‐chip filters. The chip is fabricated on a 6.5‐mm² die using a standard 0.25‐μm CMOS technology. Experimental results show an in‐band image‐rejection ratio of 40 dB, an IIP3 of ?5 dBm, and a sensitivity of ?77 dBm for the Bluetooth mode when the losses from the external components are compensated. It consumes 42 mA in receive π/4‐diffrential quadrature phase‐shift keying (π/4‐DQPSK) mode of 8 Mb/s, 35 mA in receive GFSK mode of 1 Mb/s, and 32 mA in transmit mode from a 2.5‐V supply. These results indicate that the architecture and circuits are adaptable to the implementation of a low‐cost, multi‐mode, high‐speed wireless personal area network.     

可变带宽OTA—C连续时间低通滤波器设计

实现了一种全集成可变带宽中频宽带低通滤波器,讨论分析了跨导放大器-电容（OTAc）连续时间型滤波器的结构、设计和具体实现,使用外部可编程电路对所设计滤波器带宽进行控制,并利用ADS软件进行电路设计和仿真验证。仿真结果表明,该滤波器带宽的可调范围为1～26MHz,阻带抑制率大于35dB,带内波纹小于0．5dB,采用1．8V电源,TSMC 0．18μm CMOS工艺库仿真,功耗小于21mw,频响曲线接近理想状态。     

Reconfigurable Frequency Response Masking Filters for Software Radio Channelization

Low complexity and reconfigurability are two key requirements of channel filters in a software defined radio receiver. A new reconfigurable architecture based on frequency response masking (FRM) technique for the implementation of channel filters is proposed in this paper. Our architecture offers reconfigurability at filter and architecture levels, in addition to the inherent low complexity offered by the FRM technique. The proposed reconfigurable filter has been synthesized on 0.18- CMOS technology and implemented and tested on Virtex-II 2v3000ff1152-4 field-programmable gate array. Synthesis results show that the proposed channel filter offers average area and power reductions of 53.6% and 57.6%, respectively ,with average improvement in speed of 47.6% compared to other reconfigurable filters in literature.     

A 200 MHz CMOS Q-enhanced LC bandpass filter

This paper presents design techniques and performance bounds for implementing Q-enhanced, LC bandpass filters in silicon IC technologies. These filters offer significant advantages over switched capacitor and Gm-C based designs, including higher frequency of operation and lower power consumption for a given dynamic range. A prototype 200 MHz, fourth-order filter implemented in a 2 μm n-well CMOS process is described, and measured performance is compared with theoretical predictions. The prototype filter operates at a selectivity Q of 100 and draws less than 8 mA when operating from 3 to 5 V supplies, making it potentially suitable for use as a first IF filter in modern cellular and PCS receivers     

A 1.8-V operation RF CMOS transceiver for 2.4-GHz-band GFSK applications

This paper describes a single-chip RF transceiver LSI for 2.4-GHz-band Gaussian frequency shift-keying applications, such as Bluetooth. This chip uses a 0.18-/spl mu/m bulk CMOS process for lower current consumption. The LSI consists of almost all the required RF and IF building blocks: a transmit/receive antenna switch, a power amplifier, a low noise amplifier, an image rejection mixer, channel-selection filters, a limiter, a received signal strength indicator, a frequency discriminator, a voltage controlled oscillator, and a phase-locked loop synthesizer. The bandpass filter for channel selection was difficult to achieve since it operates at a low supply voltage. However, because large interference is roughly rejected at the output of the image rejection mixer and a wide-input-range bandpass filter with an optimized input bias is realized, the transceiver can operate at a supply voltage of 1.8 V. In the IF section, we adopted a circuit design using the minimum number of passive elements, resistors and capacitors, for a lower chip area of 10.2 mm/sup 2/.     

Low-cost CMOS pulse generator for UWB systems

The design of a CMOS ultra-wideband (UWB) pulse generator for impulse radio system transmission in the 3.1-10.6 GHz frequency band is presented. The pulse generator uses an elementary pulse combiner, which appears to be well suited to tune the synthesised pulse. The generator is designed with no inductors or external filter in order to reduce the die area and the production cost. Simulations with a standard 0.13 mum CMOS design kit show a 600 mV_pp pulse that satisfies the FCC regulation mask and a power consumption of 2.64 mW with a 100 MHz pulse repetition frequency.     

Image-rejection CMOS low-noise amplifier design optimization techniques

This paper reviews and analyzes two reported image-rejection (IR) low-noise amplifier (LNA) design techniques based on CMOS technology, i.e., the second-order active notch filer and third-order passive notch filter. The analyses and discussions are based on the quality factor of filters and the ability of the frequency control. As the solution to deal with the suitable on-chip filter, this paper proposes a new notch-filter topology that can overcome the limitations of the two previous reported studies. In addition, the LNA design method satisfying the power-cons-trained simultaneous noise and input matching, as well as the linearity optimization conditions is introduced. By using the proposed notch filter and proposed design methodology, an IR LNA used in the superheterodyne architecture is implemented. The proposed IR LNA, designed based on 0.18-mum CMOS technology with total current dissipation of 4 mA under 3-V supply voltage, is optimized for a 5.25-GHz wireless local area network with IF frequency of 500-MHz applications. The measurement results show 20.5-dB power gain, lower than 1.5-dB noise figure, -5-dBm input-referred third-order intercept point and an IR of 26 dB