Copper interconnect electromigration behaviors in various structures and lifetime improvement by cap/dielectric interface treatment

Copper interconnect electromigration performance was examined in various structures and three low-k materials (k = 2.65–3.6) using advanced BEOL technology. Strong current dependence effect on electromigration lifetime in three levels via terminated metal lines structure was shown. Moreover, different process approach will lead to different EM behavior and related failure mode. Multi-modality electromigration behavior of Cu dual damascene interconnects were studied. Both Superposition and Weak-Link models were used for statistical determination of lifetimes of each failure models (Statistical method). Results were correlated to the lifetimes of respective failure models physically identified according to resistance time evolution behaviors (Physical method). Good agreement was achieved. Various testing structures are designed to identify the EM failure modes. Extensive failure analysis was carried out to understand the failure phenomena of various test structures. The activation energies of failure modes were calculated. The weak links of interconnect system were also identified. A significant improvement of electromigration (EM) lifetime is achieved by modification of the pre-clean step before cap-layer deposition and by changing Cu cap/dielectric materials. A possible mechanism for EM lifetime enhancement was proposed. Cu-silicide formation before cap-layer deposition and adhesion of Cu/cap interface were found to be critical factors in controlling Cu electromigration reliability. The adhesion of the Cu/cap interface can be directly correlated to electromigration MTF and activation energy. Results of present study suggest that interface of Cu interconnects is the key factor for EM performance for advanced BEOL technology design rules.     

Thermomechanical response and stress analysis of copper interconnects

This study is devoted to thermomechanical response and modeling of copper thin films and interconnects. The constitutive behavior of encapsulated copper film is first studied by fitting the experimentally measured stress-temperature curves during thermal cycling. Significant strain hardening is found to exist. Within the continuum plasticity framework, the measured stress-temperature response can only be described with a kinematic hardening model. The constitutive model is subsequently used for numerical thermomechanical modeling of Cu interconnect structures using the finite element method. The numerical analysis uses the generalized plane strain model for simulating long metal lines embedded within the dielectric above a silicon substrate. Various combinations of oxide and polymer-based low-k dielectric schemes, with and without thin barrier layers surrounding the Cu line, are considered. Attention is devoted to the thermal stress and strain fields and their dependency on material properties, geometry, and modeling details. Salient features are compared with those in traditional aluminum interconnects. Practical implications in the reliability issues for modern copper/low-k dielectric interconnect systems are discussed.     

A power-optimal repeater insertion methodology for global interconnects in nanometer designs

This paper addresses the problem of power dissipation during the buffer insertion phase of interconnect performance optimization. It is shown that the interconnect delay is actually very shallow with respect to both the repeater size and separation close to the minimum point. A methodology is developed to calculate the repeater size and interconnect length which minimizes the total interconnect power dissipation for any given delay penalty. This methodology is used to calculate the power-optimal buffering schemes for various ITRS technology nodes for 5% delay penalty. Furthermore, this methodology is also used to quantify the relative importance of the various components of the power dissipation for power-optimal solutions for various technology nodes.     

Methodology for characterization of high-speed multi-conductor metal interconnections and evaluation of measurement errors

Analysis and design of interconnects in high speed integrated circuits and systems involves models in the form of multiconductor transmission lines. The fundamental parameters of those models are matrices of capacitance, (C), inductance, (L), resistance, (R), and conductance (G). We present a methodology for measurement of entries in capacitance matrix. The entries of capacitance matrices can be calculated using numerical solvers of electrostatic fields established under the assumption of suitable biasing of interconnect structures. Numerical calculations of complete field equations are very complex and expensive in terms of computer time, therefore several approximations are made in constructing interconnect dedicated software packages available on the market. Because of these approximations it is necessary to validate the calculations via measurements. Calculation of the off-diagonal entries of capacitance matrix from measurements of "two-terminal" capacitances is strongly corrupted by the measuring errors. The method involves direct capacitance measurement in multi-conductor structures and provides analysis of accuracy.     

Improved a priori interconnect predictions and technology extrapolation in the GTX system

A priori interconnect prediction and technology extrapolation are closely intertwined. Interconnect predictions are at the core of technology extrapolation models of achievable system power, area density, and speed. Technology extrapolation, in turn, informs a priori interconnect prediction via models of interconnect technology and interconnect optimizations. In this paper, we address the linkage between a priori interconnect prediction and technology extrapolation in two ways. First, we describe how rapid changes in technology, as well as rapid evolution of prediction methods, require a dynamic and flexible framework for technology extrapolation. We then develop a new tool, the GSRC technology extrapolation system (GTX), which allows capture of such knowledge and rapid development of new studies. Second, we identify several "nontraditional" facets of interconnect prediction and quantify their impact on key technology extrapolations. In particular, we explore the effects of interconnect design optimizations such as shield insertion, repeater sizing and repeater staggering, as well as modeling choices for RLC interconnects.     

Thermomechanical failures in microelectronic interconnects

Thermomechanical fatigue failures are an important class of failures in microelectronic interconnect structures. Thermomechanical stresses arise from differences in the coefficients of thermal expansion of the various materials comprising a microelectronics circuit. Polymer dielectrics and adhesives have larger coefficients of expansion than metal conductors. Dielectrics and adhesives may also exhibit large anisotropy in the coefficient of expansion, producing significant thermomechanical stresses in vias or other metal interconnect structures. During ambient thermal cycling or operational power dissipation, cyclic stresses are induced, which cause fatigue failures. The basic elements of thermomechanical fatigue behavior of microelectronic interconnect structures, such as lines and vias, are presented in this paper. In addition, a case study illustrating many of the concepts is presented for a complex 3-D interconnect.     

A Model for Understanding Electromigration-Induced Void Evolution in Dual-Inlaid Cu Interconnect Structures

Electromigration-induced void evolution in various dual-inlaid copper (Cu) interconnect structures was simulated by applying a phenomenological model assisted by Monte Carlo-based simulations, considering the redistribution of heterogeneously nucleated voids and/or pre-existing vacancy clusters at the Cu/dielectric cap interface during electromigration. The results indicate that this model can qualitatively explain the electromigration-induced void evolution observed during experimental in situ secondary-electron microscopy (SEM) investigations as well as in various other reported studies. The electromigration mechanism in Cu interconnect structures and differences in the peculiar electromigration-induced void evolution in various dual-inlaid Cu interconnect structures can be clearly understood based on this model. These findings warrant reinvestigation of technologically important electromigration mechanisms by developing rigorous models based on similar concepts.     

Loop-based interconnect modeling and optimization approach for multigigahertz clock network design

A highly efficient loop-based interconnect modeling methodology is proposed for multigigahertz clock network design and optimization. Closed-form loop resistance and inductance models are proposed for fully shielded global clock interconnect structures, which capture high-frequency effects including inductance and proximity effects. The models are validated through comparisons with electromagnetic simulations and measured data taken from a Power4 chip. This modeling methodology greatly improves the clock interconnect simulation efficiency and enables fast physical design exploration. Examples of interconnect performance optimization are demonstrated and design guidelines are proposed.     

Field-Based Capacitance Modeling for Sub-65-nm On-Chip Interconnect

Back-end-of-the-line (BEOL) interconnect becomes a limiting factor to circuit performance in scaled complementary metal–oxide–semiconductor design. To accurately extract its paratactic capacitance for circuit simulation, compact models should be scalable with wire geometries and should capture the latest technology advances, such as the air gap and Cu diffusion barrier. This paper achieves these goals based on the distribution of the electric field in on-chip BEOL structures. By decomposing the electric field into various regions, the proposed method physically solves each basic capacitance component into a closed-form solution; the total ground and coupling capacitances are then the sum of all related components. Such a component-based approach is convenient in incorporating new interconnect structures. Its physics basis minimizes the complexity and the error in a traditional model fitting process. Compared with Raphael simulations at the 45-nm node, the new compact model accurately predicts the capacitance value, even in the presence of the air gap and diffusion barrier, covering a wide range of BEOL dimensions. The complete set of equations will be implemented at http://www.eas.asu.edu/~ptm.      

一种用于提取超大规模集成电路电容的新型库查找法

提出了八种节点电容典型结构用以建立电容模型库,并阐明了这八种结构可以提取大多数VLSI互连线的电容参数,给出了这些结构的拟合公式.采用该库查找法计算的互连线电容结果与FastCap所得结果非常吻合.由于电容是直接代入拟合公式计算得到的,所以计算速度非常快.     

An interconnect-centric design flow for nanometer technologies

As the integrated circuits (ICs) are scaled into nanometer dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. This paper presents the ongoing research effort at UCLA in developing an interconnect-centric design flow, including interconnect planning, interconnect synthesis, and interconnect layout, which allows interconnect design and optimization to be properly considered at every level of the design process. Efficient interconnecter performance estimation models and tools at various levels are also developed to support such an interconnect-centric design flow     

Inductance model and analysis methodology for high-speed on-chip interconnect

With operating frequencies entering the multi-gigahertz range, inductance has become an important consideration in the design and analysis of on-chip interconnects. In this paper, we present an accurate and efficient inductance modeling and analysis methodology for high-performance interconnect. We determine the critical elements for a PEEC based model by analyzing the current flow in the power grid and signal interconnect. The proposed model includes distributed interconnect resistance, inductance and capacitance, device decoupling capacitances, quiescent switching currents in the grid, pad connections, and pad/package inductance. We propose an efficient methodology for extracting these elements, using statistical models for on-chip decoupling capacitance and switching currents. Simulation results show the importance of various elements for accurate inductance analysis. We also demonstrate the accuracy of the proposed model compared to the traditional loop-based inductance approach. Since the proposed model can consist of hundreds of thousands of RLC elements, and a fully dense mutual inductance matrix, we propose a number of acceleration techniques that enable efficient analysis of large interconnect structures.     

三维互连中光刻及晶圆级键合技术的挑战、趋势和解决方案

基于它的技术优势三维集成技术正在不断地被应用到新的产品中,也包括被应用到消费电子产品里。N时也对许多工艺提出了新的要求,其中也包括光刻和晶圆级键合。三维集成技术还是需要光刻工艺来完成图形的转换．为此．讨论了三维集成工艺对工艺设备和技术提出的挑战。介绍了SUSS公司与三维技术相关的产品。着重讨论与三维集成工艺相关的光刻和键合工艺。描述了三维集成对它们提出的挑战以及目前已有的解决方案和前景。并介绍一款新的具有0．25汕m对准精度的接近接触式光刻机。     

Interconnect and substrate modeling and analysis: an overview

Accurate models for on-chip metal interconnect, silicon substrate, and packaging have become necessary for accurate simulation of high-performance ULSI circuits and high-speed RF designs. An overview of the hierarchy of techniques used to model and simulate these structures is given. While not an exhaustive summary, the purpose of the paper is to give the designer fundamental and practical understanding of principles used in modeling and analysis. The range of techniques from three-dimensional (3-D) modeling to quasi-3-D to transmission lines are analyzed, and their importance and impact are described. A modeling strategy that can include various kinds of modeling techniques and nonlinear devices in one simulation is also described     

Effects of inductance on the propagation delay and repeaterinsertion in VLSI circuits

A closed-form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 5% of dynamic circuit simulations for a wide range of RLC loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC line can be over 35% for current on-chip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for RC lines approaches a linear dependence as inductance effects increase. On-chip inductance is therefore expected to have a profound effect on traditional high-performance integrated circuit (IC) design methodologies. The closed-form delay model is applied to the problem of repeater insertion in RLC interconnect. Closed-form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. RC models can create errors of up to 30% in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the RC and RLC models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in high-performance very large scale integration (VLSI) design methodologies will increase as technologies scale     

Measurement and characterization of multilayered interconnectcapacitance for deep-submicron VLSI technology

This paper presents the measurement and characterization of multilayered interconnect capacitances for a 0.35-μm CMOS logic technology, which become a critical circuit limitation to high performance VLSI design. To measure multilayered capacitances of nonstacked, stacked, and orthogonally crossing interconnect lines, new test structures and measurement methods are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies. This study shows that the calibration method considerably improves the accuracy of simulation results compared with measured results     

Optimization study of VLSI interconnect parameters

In this paper, we present the results of optimizing interconnect parameters to satisfy chip-level targets in future device generations. The optimization approach used is based on existing system-level models and can optimize the number of wire levels, speed, chip size, and power in sequence, with the optimization variables being all interconnect parameters such as pitches, thicknesses, etc. We also study the trade-offs resulting from various interconnect process limitations and choices. The findings of this study, in brief, are: 1) while the thickness of the interlayer dielectric (ILD) can be scaled without adverse effects on speed so that the hole aspect ratio is held constant at about 3.0 across generations, it is important to provide extremely thick ILD films in excess of 4 pm in the upper wire levels, 2) while the maximum wire thickness can be safely held to about 2 μm in the upper wire levels, extremely thin wires of less than 0.1 pm thickness will soon be needed in the lower wire levels to reduce capacitance, 3) while wire resistivity reduction is desirable it is much more important to reduce the ILD dielectric constant aggressively, and 4) chip size constraints can impact the speed extremely and need to considered carefully. These results can be used to construct an optimal interconnect technology roadmap and can be an invaluable aid in guiding interconnect process development     

超高阶的RLGC互连线时域状态空间模型及其研究

在互连线的建模方面,无论是考虑频变或工艺参数变化还是考虑降解,都需要一个精确的原始模型。它不仅使各种模型简化方法有个精确的起点,而且也是评估各种模型简化方法近似性能的基础。该文用直接闭合式的方法给出了一个计算复杂度为O(N)的精确的超高阶互连线RLGC时域状态空间模型,有3种形式,它是一般互连线树的基本构造元素,也是一种特殊的互连线树。该模型在形式上比文献中给出的更简洁。低阶模型与2000阶模型进行了比较,结果表明阶数较低的RLGC/RLC电路模型与分布参数电路模型相比在电路的振荡特性以及上升时间的描述上存在相当大的误差,因此在互连线树的建模中支路(包括根和叶的互连线)采用低阶原始模型值得商榷。     

Performance Modeling of Low-$k$/Cu Interconnects for 32-nm-Node and Beyond

Challenges and issues with the scaling of low-$k$/Cu interconnects in ultra-large-scale integration (ULSI) devices are reviewed, and the performance of interconnects is featured by considering the effect of the resistance and capacitance per unit interconnect length or the minimum grid length. The grid-scaled resistance–capacitance (GSRC) model is proposed to compare the interconnect performance at various technology nodes. Introduction of low-$k$ films to reduce the line capacitance improves the per-grid value of the resistance–capacitance product, however, the abrupt increment of the line resistivity due to the small-size effect consumes the benefit of the capacitance beyond 32-nm-node. We also discuss power consumption in interconnects with different low- $k$ structures based on experimental works. Continuous reduction of effective $k$-value $(K_{ rm eff})$ is needed to reduce the active power consumption. The way to reduce the interconnect resistance while keeping the interconnect reliability high is a key challenge, particularly for deeply scaled-down ULSIs.