High-speed, accurate analogue CMOS rank filter

A modular, low-voltage, analogue CMOS architecture for rank extraction based on the use of a simple, compact current amplifying cell is proposed. The circuit has a DC error of <-50 dB for inputs ranging from 100 nA to 30 μA, recovery time of <12 ns, and electronic tunability of the extracted rank     

High-speed high-precision min/max circuits in CMOS technology

New voltage-mode min/max circuits are introduced that have a simple architecture. Unlike conventional winner-take-all or source follower based schemes, the proposed circuits are characterised by reduced voltage swing at all internal nodes and by a very low output impedance, which enables them to provide high-speed and high-precision operation. Their complexity grows linearly with the number of inputs. The characterisation of a test chip prototype has provided experimental verification of these features     

An adaptive analog continuous-time CMOS biquadratic filter

An adaptive analog continuous-time biquadratic filter is realized in a 2-μm digital CMOS process for operation at 300 kHz. The biquad implements the notch, bandpass and low-pass transfer functions. The only parameter adapted is the resonant frequency of the biquad, which is identical to the notch frequency and the bandpass center frequency. The update method is based on a least-means-square algorithm which adapts the notch frequency to minimize the power at the notch filter output. The actual update is modified to reduce the circuit complexity to one biquad and one correlator. When the filter is tracking a sinusoid, this update generates a ripple-free gradient that decreases tracking error. Applications include phase-frequency detectors, FM demodulators (linear and frequency shift keying), clock extractors, and frequency acquisition aids for phase-locked loops and Costas loops. Measured results from experimental prototypes are presented. Nonidealities of an all-analog implementation are discussed, along with suggestions to improve performance     

A fully parallel CMOS analog median filter

A fully integrated CMOS implementation of a continuous-time analog median filter is presented. The median filter uses two compact analog circuits as building blocks to implement the variable delay and median detection. Median detectors are based on current saturating transconductance comparators, while the time delay is implemented using first-order all-pass filters. Both circuits allow modular expansion for the implementation of large median filter array processors. Based on these blocks, a new fast technique for parallel image processing is presented. It is shown that an image of 91/spl times/80 pixels can be processed in less than 8 /spl mu/s using an array of median filter cells. Experimental results of a test chip prototype in 2-/spl mu/m CMOS MOSIS technology are presented.     

High-speed CMOS analog Viterbi detector for 4-PAM partial-responsesignaling

In this paper, a 1-Gb/s analog Viterbi detector based on a 4-PAM duobinary scheme is discussed with experimental results for a 0.25-μm CMOS implementation. This chip is the first analog integrated implementation of a reduced state sequence detector. Pipelining and parallel processing have been incorporated in this design for high-speed operation. Due to test equipment limitations, experimental results are given for 200-Mb/s operation while simulation results indicate a speed of 1 Gb/s. Power dissipation is 55 mW from a 2.5-V supply. The active area occupies 0.78 mm². Although a duobinary scheme has been the focus of this work for its application in optical links, this design can be readily modified or extended to other partial-response signaling schemes such as dicode and PR4     

New compact CMOS continuous-time low-Voltage analog rank-order filter architecture

A new compact CMOS continuous-time analog rank-order filter topology is presented. The hardware complexity grows linearly with the number of inputs at the rate of only two transistors per input. The implementation is based on a multiple input differential structure. The rank is programmable with the tail current source for all rank-order values from the Min to the Max case. The circuit has low voltage and low power consumption requirements. Experimental results are presented that verify the functionality and accuracy of the circuit. Simulation results show satisfactory operation in the 100-MHz frequency range for 0.5-/spl mu/m CMOS technology and using a single 1.8-V supply. Two buffered versions of the circuit and efficient techniques for reduction of corner errors are also discussed.     

A fully programmable sampled-data analog CMOS filter with transfer-function coefficients determined by timing

A CMOS analog signal processor which is as programmable as a digital one is discussed. This processor does not use known switched-capacitor techniques, nor does it contain any selectable capacitor (or resistor) arrays. Instead, it operates on a pulsewidth control principle in which the value of each branch gain is determined by the duty cycle of a single digitally controlled analog transmission gate. A 4-/spl mu/m single-poly CMOS test IC containing all the critical analog functions was designed to demonstrate this principle at sampling frequencies up to 100 kHz. All of the processors described allow individual programming of each transfer function coefficient; one also features programmable topology, and another is capable of simultaneous multiple-signal multiple-transfer-function processing. A typical integrated fully programmable biquad shows 80-dB dynamic range.     

A ranked order filter implementation for parallel analog processing

Order statistic filtering, the generalization of which is ranked order filtering, is needed for many image-processing functions including median filtering and mathematical morphology. Combining order statistic functionality with the parallel operation and local connectivity of array processing approaches such as the cellular nonlinear network model, has the potential for very high performance in image processing. This paper examines the implementation of programmable ranked order extraction with a very compact hardware realization of an analog current-mode ranked order filter. The considerable savings in the required circuit area, compared to other circuits, make it possible to use the structure as a building block in a massively parallel signal processing array. The operation of the circuit is analyzed in detail with the help of simulations and measurement results obtained from a test chip manufactured in a 0.18-/spl mu/m standard digital CMOS technology are also presented. The simulations and measurement results verify the correct operation of the circuit and show that it is very suitable for inclusion in every cell of a large parallel processor array. This makes many grayscale processing functions available with truly parallel operation and therefore very high performance.     

CMOS analog MAP decoder for (8,4) Hamming code

Design and test results for a fully integrated translinear tail-biting MAP error-control decoder are presented. Decoder designs have been reported for various applications which make use of analog computation, mostly for Viterbi-style decoders. MAP decoders are more complex, and are necessary components of powerful iterative decoding systems such as turbo codes. Analog circuits may require less area and power than digital implementations in high-speed iterative applications. Our (8, 4) Hamming decoder, implemented in an AMI 0.5-/spl mu/m process, is the first functioning CMOS analog MAP decoder. While designed to operate in subthreshold, the decoder also functions above threshold with a small performance penalty. The chip has been tested at bit rates up to 2 Mb/s, and simulations indicate a top speed of about 10 Mb/s in strong inversion. The decoder circuit size is 0.82 mm/sup 2/, and typical power consumption is 1 mW at 1 Mb/s.     

A monolithic analog video comb filter in 1.2-μm CMOS

A fully integrated comb filter for luminance/chrominance (Y/C) separation of NTSC video signals is fabricated using a standard 1.2-μm double-poly CMOS technology. This paper demonstrates its use of analog RAM structures in the realization of video line delays. Information is stored and retrieved using switched-capacitor techniques optimized for operation in a parasitic dominated environment. Fixed pattern noise is avoided through the use of serial data paths whenever possible, necessitating the use of a G_m-enhanced amplifier and techniques to improve the feedback factor. The 11.7 mm² adjustment-free circuit, which requires a single clock and reference current, dissipates 170 mW at 5 V and yields an SNR of 51 dB and frequency response flat within 1.1 dB to 4.2 MHz     

低成本CMOS阵列式高速成像系统

高速摄像是研究瞬间发生的物理和化学现象的重要手段之一.针对碰撞过程,提出了应用低成本CMOS阵列式成像传感器构建高速摄像系统.成像阵列由16个可更换的CMOS单元组成,接在主板上.为了进行同步控制,实验研究了CMOS传感器的工作时序;通过延时器,使阵列式火花源分时闪光,并在CMOS快门打开的时间段内完成.实验表明,该系统可以实现对碰撞等瞬间发生过程的拍摄,为相关研究提供基础.     

High-speed dynamic reference voltage (DRV) CMOS/ECL interfacecircuits

This paper introduces a circuit technique to increase the operating speed of CMOS/ECL interface circuits. The technique is based on shifting the reference voltage dynamically to follow the ECL input signal. HSPICE simulation results based on a 0.8-μm BiCMOS technology show the advantages of DRV CMOS/ECL in terms of speed and noise margins. An analytical delay model which fits HSPICE simulation results is addressed. The error between the model and the circuit simulator is within 4%     

High-performance designs with CMOS analog standard cells

The authors describe an approach to the design of complex analog functions comprising the major functions normally encountered in analog systems using a library of 3-/spl mu/m CMOS analog cells. It is shown that through the use of a fixed-height cell system and a predefined connection system, circuits can be designed that suffer little, if any, area penalty when compared to a full custom layout. In addition, the overall system performance achieved can equal that of some full custom designs.     

Adaptive two-pass rank order filter to remove impulse noise in highly corrupted images

In this paper, we present an adaptive two-pass rank order filter to remove impulse noise in highly corrupted images. When the noise ratio is high, rank order filters, such as the median filter for example, can produce unsatisfactory results. Better results can be obtained by applying the filter twice, which we call two-pass filtering. To further improve the performance, we develop an adaptive two-pass rank order filter. Between the passes of filtering, an adaptive process is used to detect irregularities in the spatial distribution of the estimated impulse noise. The adaptive process then selectively replaces some pixels changed by the first pass of filtering with their original observed pixel values. These pixels are then kept unchanged during the second filtering. In combination, the adaptive process and the second filter eliminate more impulse noise and restore some pixels that are mistakenly altered by the first filtering. As a final result, the reconstructed image maintains a higher degree of fidelity and has a smaller amount of noise. The idea of adaptive two-pass processing can be applied to many rank order filters, such as a center-weighted median filter (CWMF), adaptive CWMF, lower-upper-middle filter, and soft-decision rank-order-mean filter. Results from computer simulations are used to demonstrate the performance of this type of adaptation using a number of basic rank order filters.     

On (n, n-1) convolutional codes with low trellis complexity

We show that the state complexity profile of a convolutional code C is the same as that of the reciprocal of the dual code of C in case that minimal encoders for both codes are used. Then, we propose an optimum permutation for any given (n, n-1) binary convolutional code that will yield an equivalent code with the lowest state complexity. With this permutation, we are able to find many (n, n-1) binary convolutional codes which are better than punctured convolutional codes of the same code rate and memory size by either lower decoding complexity or better weight spectra     

High-speed CMOS demultiplexer with redundant multi-valued logic

This paper describes an 11-Gb/s CMOS demultiplexer with redundant multi-valued logic. The proposed circuit receives serial binary data which is converted to parallel redundant multi-valued data. The converted data are reconverted to parallel binary data. By the redundant multi-valued data conversion, the redundant multi-valued logic makes it possible to achieve higher operating speeds than that of a conventional binary logic. The implemented demultiplexer consists of eight integrators. The circuit is designed with a 0.35?µm standard CMOS process. The validity and effectiveness are verified through HSPICE simulation. The demultiplexer is achieved to the maximum data rate of 11-Gb/s and the average power consumption of 69.43?mW. This circuit is expected to operate at a higher speed than 11-Gb/s in the deep-submicron process of the high operating frequency.     

An analog median filter with fuzzy adaptation

The implementation of an analog median filter with a fuzzy adaptation mechanism is discussed. The adaptive median filter is based on transconductance comparators, which saturation current is used to adapt the local weight operator. All the simulations were made using a BSIM3 Level 49 model and 1.5 μm MOSIS technology parameters.     

一种应用于IEEE 802.11 b/g/n无线局域网收发机的CMOS模拟基带电路

本文提出了一种应用于直接变频无线局域网收发机的模拟基带电路,该电路采用标准的0.13微米CMOS工艺实现,包括了采用有源RC方式实现的接收4阶椭圆低通滤波器、发射3阶切比雪夫低通滤波器、包含直流失调消除伺服环路的接收可变增益放大器及片上输出缓冲器。芯片面积共1.26平方毫米。接收基带链路增益可在-11dB至49dB间以2dB步长调节。相应地,基带接收输入等效噪声电压（IRN）在50 nV/sqrt(Hz) 至30.2 nV/ sqrt(Hz)间变化而带内输入三阶交调（IIP3）在21dBm至-41dBm间变化。接收及发射低通滤波器的转折频率可在5MHz、10MHz及20MHz之间选择以符合包含802.11b/g/n的多种标准的要求。接收基带I、Q两路的增益可在-1.6dB至0.9dB之间以0.1dB的步长分别调节以实现发射IQ增益失调校正。通过采用基于相同积分器的椭圆滤波器综合技术及作用于电容阵列的全局补偿技术,接收滤波器的功耗显著降低。工作于1.2V电源电压时,整个芯片的基带接收及发射链路分别消耗26.8mA及8mA电流。