The effects of low temperature buffer layer on the growth of pure Ge on Si(001)

We investigated the effects of low temperature (LT) Ge buffer layers on the two-step Ge growth by varying the thickness of buffer layers. Whereas the two-step Ge layers using thin (< 40 nm) Ge buffer layers were roughened due to the formation of SiGe alloy, pure and flat Ge layers were grown by using thick (> 50 nm) LT Ge buffer layers. The lowest threading dislocation density of 1.2 × 10⁶ cm⁻² was obtained when 80-nm-thick LT Ge buffer layer was used. We concluded that the minimum thickness of buffer layer was required to grow uniform two-step Ge layers on Si and its quality was subject to the thickness of buffer layer.     

Growth of high Ge content SiGe on (110) oriented Si wafers

Growth of high (above 40%) Ge content SiGe by applying silane and dichlorosilane as Si precursors on (110) Si is investigated. In the case of silane based processes Ge concentration is ~ 20% higher, whereas for dichlorosilane based processes it is ~ 30% lower on (110) Si compared to (100) Si. The morphology of the grown layers is found to be dependent on Ge concentration, layer thickness and process temperature. Use of optimized deposition parameters and adequate thickness results in high quality strained SiGe layers. Integration of high Ge content SiGe layers in multiple gate filed-effect transistor structures shows the expected differences in Ge content on the different Si planes forming Si fin. These differences can be avoided by adjusting the fin orientation on the Si wafer resulting in equal planes on the fin's top and sidewalls. When the investigated SiGe layers are incorporated in the buried channel field effect transistor structures on (110) Si wafers a significant thickening at the active windows edge is observed. It is speculated that this effect is connected with elastic SiGe relaxation caused by a non optimized process temperature.     

Si_(0.75)Ge_(0.25)虚衬底上应变补偿Si/Si_(0.62)Ge_(0.38)量子阱发光

由于Si/SiGe异质结构的带阶差主要发生在价带,为实现高效率的发光,本文从理论上设计了在硅基Si1-xGex虚衬底上外延应变补偿的Si/S1-yGey(y>x)量子阱的能带结构,将量子阱对电子的限制势垒提高到100meV以上。在实验上,采用300℃生长的Ge量子点插入层,制备出薄的SiGe驰豫缓冲层(虚衬底),表面Ge组份达到0.25,表面粗糙度小于2nm,驰豫度接近100%。在我们制备的SiGe缓冲层上外延了应变补偿SiGe/Si多量子阱结构,并初步研究了其发光特性。     

High quality Ge epitaxial layers on Si by ultrahigh vacuum chemical vapor deposition

Flat, relaxed Ge epitaxial layers with low threading dislocation density (TDD) of 1.94 × 10⁶ cm^− 2 were grown on Si(001) by ultrahigh vacuum chemical vapor deposition. High temperature Ge growth at 500 °C on 45 nm low temperature (LT) Ge buffer layer grown at 300 °C ensured the growth of a flat surface with RMS roughness of 1 nm; however, the growth at 650 °C resulted in rough intermixed SiGe layer irrespective of the use of low temperature Ge buffer layer due to the roughening of LT Ge buffer layer during the temperature ramp and subsequent severe surface diffusion at high temperatures. Two-dimensional Ge layer grown at LT was very crucial in achieving low TDD Ge epitaxial film suitable for device applications.     

Structure and surface morphology of Si1 — x Ge x layers grown on Si/sapphire by molecular beam epitaxy using a sublimation silicon source and gaseous germanium source

Si_{1 ? x} Ge _x epilayers have been grown on silicon-on-sapphire structures by molecular beam epitaxy using a sublimation silicon source and gaseous germanium source. Si_{1 ? x} Ge _x layers grown directly on sapphire substrates had poorer structural perfection, so Si buffer layers were used in subsequent growth runs. Using X-ray photoelectron spectroscopy, we determined the concentration-depth profiles of Si, Ge, and background impurities across the layers. Varying the Si buffer thickness in the range 50–300 nm was shown to have no effect on the structure of the SiGe layers. Single-crystal SiGe layers were obtained at substrate temperatures in the range 360–410°C. Varying the germanium concentration in the range 5–25% had no effect on the structure of the layers but slightly increased their roughness.     

SiGe-based FETs: buffer issues and device results

SiGe quantum well structures gain increasing interest in the Si technology. The preparation of a Si channel or a Ge-rich or even a pure Ge channel with a respective two-dimensional carrier gas opens the attractive possibility to fabricate high performance n- or p-type field effect transistors. For both device types, a virtual substrate surface is required which is created by a strain relieved buffer layer grown on a Si standard wafer. The paper reviews various approaches of SiGe buffers including special attempts to reduce the thickness and to improve the quality. N- and p-type modulation-doped field-effect transistors are presented which show comparably good device characteristics and cut-off frequencies in the range of 100–120 GHz.     

High strain embedded-SiGe via low temperature reduced pressure chemical vapor deposition

Performance improvement of strained p-type metal oxide semiconductor field effect transistors (p-MOSFETs) via embedded SiGe (e-SiGe) is well established. Strain scaling of p-MOSFETs since 90 nm complementary metal oxide semiconductor node has been accomplished by increasing Ge content in e-SiGe from nominally < 20% in 90 nm p-MOSFETs to > 35% Ge in 32 nm p-MOSFETs. Further strain enhancement for 22 nm and beyond p-MOSFETs is required due to disproportionate reduction in device area per generation caused by non-scaled gate length. Relaxation of SiGe with > 35% Ge during epitaxial growth and subsequent processing is a major concern. Specifically low temperature growth is required to achieve meta-stable pseudomorphic SiGe film with high Ge%. Currently, selective SiGe epitaxial film in reduced pressure chemical vapor deposition (RPCVD) epitaxy is grown with conventional Si gas precursors and co-flow etch using HCl at temperatures higher than 625 °C. At temperatures lower than 625 °C in RPCVD epitaxy, however, HCl has negligible etch capability making selectivity difficult to achieve during epitaxial growth. Hence, cyclic deposit and etch epitaxial growth in conjunction with a low temperature etching chemistry is desirable to achieve selectivity at temperatures lower than 625 °C. In this paper, we apply the above concept to achieve selective growth of high strain SiGe (> 35%) at 500 °C on test patterns corresponding to 65 nm node. SiGe is grown non-selectively first at 500 °C with high order of silane as Si source, and Germane as Ge source followed by an etching chemistry also at 500 °C to achieve selectivity. In addition, the growth rate of SiGe epitaxial film and the Ge concentration in the deposited epitaxial film were studied as a function of Si precursor flow; the effect of HCl introduction on Ge concentration and film growth rate was discussed.     

UV Raman spectroscopy of group IV nanocrystals embedded in a SiO<Subscript>2</Subscript> matrix

Nanostructures of both Ge nanocrystals formed by thermal oxidation of SiGe layers, and SiGe nanocrystals formed by crystallization of amorphous SiGe nanoparticles deposited by LPCVD have been analyzed by Raman spectroscopy. The nanostructures are formed on a silicon substrate. Raman spectra have been acquired with visible (514.5 nm) and UV (325 nm) excitation lines. When the amount of material is very small, as it has happens in these nanostructures, the visible line is not able to excite the characteristic peaks of the Ge or SiGe in the Raman spectrum; instead the Si second order spectrum of the substrate appears and it can be misinterpreted by attributing it to the Ge–Ge band associated with the nanocrystals. In this work, the use of UV excitation has been demonstrated to enhance the sensitivity respect to the conventional visible excitation, allowing the characteristic peaks of the Ge or SiGe nanocrystals to appear in the spectrum. We attributed this effect to the resonance effects.     

Growth of high-quality relaxed SiGe films with an intermediate Si1−yCy layer for strained Si n-MOSFETs

High quality and thin relaxed SiGe films were grown on Si (0 0 1) using ultra high vacuum chemical vapor deposition (UHV/CVD) by employing an intermediate Si_1−yC_y layer. The Si_1−yC_y/SiGe bilayer was found to change mechanism of relaxation in the SiGe overlayer. Compared with the samples with a Si layer, the equilibrium critical thickness of top SiGe films with rough surface by introducing an intermediate Si_0.986C_0.014 layer are drastically reduced; this result was attributed to larger tensile stress in the inserted Si_0.986C_0.014 layer. With a 210-nm-thick Si_0.8Ge_0.2 overlayer, this Si_0.8Ge_0.2/Si_0.986C_0.014/Si_0.8Ge_0.2 heterostructure has a threading dislocation density (TDs) less than 1 × 10⁵ cm⁻² and a residual strain of 30%. The root mean square (RMS) of surface roughness for this sample was measured to be about 1.8 nm. In this SiGe/Si_1−yC_y/SiGe structure, C atoms in the intermediate Si layer will improve the relaxation of thin SiGe overlayer, however, the relaxation for the 700-nm-thick SiGe overlayer is independent of the addition of C. The point defects rich Si_0.986C_0.014 layer plays the role to confine the misfit dislocations, which formed at the interface of the top Si_0.8Ge_0.2 and the Si_0.986C_0.014 layer, and blocked the propagation of TDs. Strained-Si n-channel metal-oxide-semiconductor transistors (n-MOSFETs) with a 210-nm-thick Si_0.8Ge_0.2 overlayers as buffer were fabricated and examined. Drain current and effective electron mobility for the strained-Si device with this novel substrate technology was found to be 100 and 63% higher than that of control Si device. Our results show that thin relaxed Si_0.8Ge_0.2 films with the intermediate Si_0.986C_0.014 layer serve as good candidates for high-speed strained-Si devices.     

Formation of uniaxially strained SiGe by selective ion implantation technique

Uniaxially strained SiGe layers were fabricated with a newly developed selective-ion-implantation technique. The SiGe layer was grown on the Si substrate, into which laterally selective ion-implantation with stripe pattern was carried out prior to the SiGe growth. A strain-relaxation of the SiGe layer was largely enhanced due to ion-implantation-induced defects selectively in the ion-implanted area while it was hardly enhanced in the neighboring unimplanted area. However, micro-Raman mapping and X-ray diffraction reciprocal space mapping measurements obviously revealed that the relaxed SiGe in the implanted area remarkably influenced a strain state of the neighboring strained SiGe in the unimplanted area, that is, the strain along the stripe line direction was highly relieved due to the stress caused by the neighboring relaxed SiGe while the strain in the direction perpendicular to the line was well maintained. As a result, highly asymmetric strain state, that is, uniaxial strain was realized, where 4 times different relaxation ratios in the two directions were observed. These results indicate that the selective-ion-implantation technique developed in this study has a high potential to realize uniaxially strained Si/Ge channel devices with high mobility.     

Raman scattering studies of ultrashallow Sb implants in strained Si

Sheet resistance (R _s) reductions are presented for antimony doped layers in strained Si. We use micro-Raman spectroscopy to characterise the impact of a low energy (2 keV) Sb implantation into a thin strained Si layer on the crystalline quality and resultant stress in the strained Si. The use of 325 nm UV laser light enables us to extract information from the top ∼9 nm of the strained Si layer. Prior to implantation the Si layer is fully strained with a tensile stress value ∼1.41 GPa, in agreement with the calculated theoretical maximum on a strain relaxed buffer with 17% Ge content. There is a clear decrease in the intensity of the Si Raman signal following Sb implantation. The lattice damage and lattice recovery achieved by subsequent rapid thermal anneal (RTA) is quantified using the amplitude and full width at half maximum (FWHM) of the crystalline Si peak. The shift of the Raman Si peak is a key parameter in the interpretation of the spectra. The ion-implanted sample is studied in terms of a phonon coherence length confinement model. Carrier concentration effects are seen to play a role in the Raman shift following electrical activation of the Sb atoms by RTA.     

Geometry dependent nucleation mechanism for SiGe islands grown on pit-patterned Si(001) substrates

SiGe islands grown on pit-patterned Si(001) substrates show significant dependence on the surface geometry of the substrate, especially when the period of the patterning is reduced to below 300 nm. With different geometry of pit-patterned substrates, SiGe islands are observed to preferentially nucleate at the bottom of shallow pits after a ripple formation of the SiGe wetting layer, or at the top terrace when the pits are deep and steep.     

GexSi1-x/Si中应变的会聚束电子衍射研究

介绍了会聚束电子衍射（ＣＢＥＤ）技术与计算机模拟相结合测定ＧｅｘＳｉ１－ｘ／Ｓｉ化学梯度层中应变分布的实验结果,提供了一种高空间分辨率,高灵敏度,且适用于任何材料系中微区晶格常数测定及应变分布研究的技术途径。     

Observation of free surface-induced bending upon nanopatterning of ultrathin strained silicon layer

We provide evidence of nanopatterning-induced bending of an ultrathin tensile strained silicon layer directly on oxide. This strained layer is achieved through the epitaxial growth of silicon on a Si(0.84)Ge(0.16) virtual substrate and subsequent transfer onto a SiO(2)-capped silicon substrate by combining hydrophilic wafer bonding and the ion-cut process. Using high resolution transmission electron microscopy, we found that the upper face of the strained silicon nanostructures fabricated from the obtained heterostructure using electron beam lithography and dry reactive ion etching displays a concave shape. This bending results from the free-surface-induced strain relaxation, which implies lattice out-of-plane expansion near the edges and concomitant contraction at the center. For a ～ 110 nm × 400 nm × 20 nm nanostructure, the bending is associated with an angle of 1.5° between the [Formula: see text] vertical atomic planes at the edges of the ～ 110 nm side. No bending is, however, observed at the strained Si/SiO(2) interface. This phenomenon cannot be explained by the classical Stoney's formula or related formulations developed for nanoscale thin films. Here we employed a continuum mechanical approach to describe these observations using three-dimensional numerical calculations of relaxation-induced lattice displacements.     

Generation of uniaxial tensile strain of over 1% on a Ge substrate for short-channel strained Ge n-type Metal-Insulator-Semiconductor Field-Effect Transistors with SiGe stressors

Tensile strain of over 1% in Ge stripes sandwiched between a pair of SiGe source-drain stressors was demonstrated. The Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET)-like structures were fabricated on a (001)-Ge substrate having SiO₂ dummy-gate stripes with widths down to 26 nm. Recess-regions adjacent to the dummy-gate stripes were formed by an anisotropic wet etching technique. A damage-free and well-controlled anisotropic wet etching process is developed in order to avoid plasma-induced damage during a conventional Reactive-ion Etching process. The SiGe stressors were epitaxially grown on the recesses to simulate strained Ge n-channel Metal-Insulator-Semiconductor Field-Effect Transistors (MISFETs) having high electron mobility. A micro-Raman spectroscopy measurement revealed tensile strain in the narrow Ge regions which became higher for narrower regions. Tensile strain of up to 1.2% was evaluated from the measurement under an assumption of uniaxial strain configuration. These results strongly suggest that higher electron mobility than the upper limit for a Si-MOSFET is obtainable in short-channel strained Ge-nMISFETs with the embedded SiGe stressors.     

Effect of Germanium content and strain on the formation of extended defects in ion implanted Silicon/Germanium

We studied the evolution of extended defects in relaxed and strained Si and SiGe structures after an amorphising implant. The investigated structures included three relaxed SiGe alloy layers with various Ge contents (20, 35 and 50 at.%), a 40 nm-thick tensely strained Si layer and a 40 nm-thick compressively strained Si_0.8Ge_0.2 layer. Concerning the compositional effects, we found that the increase of Ge concentration in relaxed SiGe structures leads to: (i) an overall decrease of the defect stability and to (ii) an enhanced {311}-to-loops transformation. As for the strain effects, it is found that: (i) Tensile strain (in Si) retards the transformation of {311} defects into loops; (ii) compressive strain (in SiGe) enhances the transformation of {311}s into loops; (iii) in all cases, the overall defect stability is not strongly modified in the presence of strain. The observed results are discussed in terms of the various mechanisms involved, including the increase of the interstitial diffusivity in relaxed SiGe alloys (with respect to Si) and the strain effects on both interstitial equilibrium concentration and defect formation energy.     

Composition and local strain mapping in Au-catalyzed axial Si/Ge nanowires

For most applications, heterostructures in nanowires (NWs) with lattice mismatched materials are required and promise certain advantages thanks to lateral strain relaxation. The formation of Si/Ge axial heterojunctions is a challenging task to obtain straight, defect free and extended NWs. And the control of the interface will determine the future device properties. This paper reports the growth and analysis of NWs consisting of an axial Si/Ge heterostructure grown by a vapor-liquid-solid process. The composition gradient and the strain distribution at the heterointerface were measured by advanced quantitative electron microscopy methods with a resolution at the nanometer scale. The transition from pure Ge to pure Si shows an exponential slope with a transition width of 21?nm for a NW diameter of 31?nm. Although diffuse, the heterointerface makes possible strain engineering along the axis of the NW. The interface is dislocation-free and a tensile out-of-plane strain is noticeable in the Ge section of the NW, indicating a lattice accommodation. Experimental results were compared to finite element calculations.     

Stranski–Krastanov growth of (Si)Ge/Si(001): transmission electron microscopy compared with segregation theory

ABSTRACT

We performed transmission electron microscopy of SiGe/Si(001) and Ge/Si(001) samples that undergo the Stranski–Krastanov transition from flat layer to island growth. With the help of quantitative X-ray maps of those layers, we have determined the total amount of deposited germanium at which islanding commences. The maximum amount of Ge buried in a flat layer amounts to 2.3 monolayers. We show by modelling that it is the strain due to the total amount of Ge atoms deposited that drives the islanding process. At 600°C [400°C], 1.62 [1.74] monolayers of Ge are expected from simulations to segregate towards the surface, the strain of which is sufficient to trigger plastic relaxation by islanding, in agreement with our electron microscope observations.

This is part of a thematic issue on Nanoscale Materials Characterisation and Modeling by Advances Microscopy Methods - EUROMAT.     

One-step Ge/Si epitaxial growth

Fabricating a low-cost virtual germanium (Ge) template by epitaxial growth of Ge films on silicon wafer with a Ge(x)Si(1-x) (0 < x < 1) graded buffer layer was demonstrated through a facile chemical vapor deposition method in one step by decomposing a hazardousless GeO(2) powder under hydrogen atmosphere without ultra-high vacuum condition and then depositing in a low-temperature region. X-ray diffraction analysis shows that the Ge film with an epitaxial relationship is along the in-plane direction of Si. The successful growth of epitaxial Ge films on Si substrate demonstrates the feasibility of integrating various functional devices on the Ge/Si substrates.     

Misfit-guided self-organization of anticorrelated ge quantum dot arrays on si nanowires

Misfit-strain guided growth of periodic quantum dot (QD) arrays in planar thin film epitaxy has been a popular nanostructure fabrication method. Engineering misfit-guided QD growth on a nanoscale substrate such as the small curvature surface of a nanowire represents a new approach to self-organized nanostructure preparation. Perhaps more profoundly, the periodic stress underlying each QD and the resulting modulation of electro-optical properties inside the nanowire backbone promise to provide a new platform for novel mechano-electronic, thermoelectronic, and optoelectronic devices. Herein, we report a first experimental demonstration of self-organized and self-limited growth of coherent, periodic Ge QDs on a one-dimensional Si nanowire substrate. Systematic characterizations reveal several distinctively different modes of Ge QD ordering on the Si nanowire substrate depending on the core diameter. In particular, Ge QD arrays on Si nanowires of around 20 nm diameter predominantly exhibit an anticorrelated pattern whose wavelength agrees with theoretical predictions. The correlated pattern can be attributed to propagation and correlation of misfit strain across the diameter of the thin nanowire substrate. The QD array growth is self-limited as the wavelength of the QDs remains unchanged even after prolonged Ge deposition. Furthermore, we demonstrate a direct kinetic transformation from a uniform Ge shell layer to discrete QD arrays by a postgrowth annealing process.