一种基于短LT码的级联编译码算法

针对实时无线通信对短纠删码的需求,提出一种短码长LT码与传统纠错码的级联方案。在综合考虑算法复杂度与纠错性能的情况下,选取RS码和卷积码的级联(RS-CC码)以构造等效删除信道,并采用实时性高的短LT码实现纠删功能。文中设计了一种适合短LT码的译码算法,同时给出了编码度分布的选取方法。仿真结果表明,与已有短喷泉码相比,文中短LT码成功译码时所需编码冗余更少,应用到级联方案后的数据传输可靠性明显提高。     

Design and development of new reconfigurable architectures for LSB/multi-bit image steganography system

The most crucial task in real-time processing of steganography algorithms is to reduce the computational delay and increase the throughput of a system. This critical issue is effectively addressed by implementing steganography methods in reconfigurable hardware. In the proposed framework, a new high-speed reconfigurable architectures have been designed for Least Significant Bit (LSB) or multi-bit based image steganography algorithm that suits Field Programmable Gate Arrays (FPGAs) or Application Specific Integrated Circuits (ASICs) implementation. The architectures are designed and instantiated to implement the complete steganography system. The proposed system is competent enough to provide larger throughput, since high degrees of pipelining and parallel operations are incorporated at the module level. The evolved architectures are realized in Xilinx Virtex-II Pro XC2V500FG256-6 FPGA device using Register Transfer Level (RTL) compliant Verilog coding and has the capacity to work in real-time at the rate of 183.48 frames/second. Prior to the FPGA/ASIC implementation, the proposed steganography system is simulated in software to validate the concepts intended to implement. The hardware implemented algorithm is tested by varying embedding bit size as well as the resolution of a cover image. As it is clear from the results presented that the projected framework is superior in speed, area and power consumption compared to other researcher’s method.     

IEEE 1451.0 standard based smart readout for multi-rate control of system

This paper presents a novel architecture for multi-rate control system with disturbance estimation and rejection using FPGA connected with sensors and actuators through IEEE 1451 standard. A signum function is used for estimation error correction. Estimated states are used to provide the control input at a rate higher or lower than the sample rate thus providing multi-rate control. An architecture is proposed to implement the proposed multi-rate controller in FPGA platform through IEEE 1451.0-2007 standard. The control scheme requires minimum analog hardware, namely comparator and digital to analog convertor and provides multi-bit resolution with multi-rate processing.     

Bitstream decoding and SEU-induced failure analysis in SRAM-based FPGAs

Reconfigurable SRAM-based FPGAs are highly susceptible to radiation induced single-event upsets (SEUs) in space applications.The bit flip in FPGAs configuration memory may alter user circuit permanently without proper bitstream reparation,which is a completely different phenomenon from upsets in traditional memory devices.It is important to find the relationship between a programmable resource and corresponding control bit in order to understand the impact of this effect.In this paper,a method is proposed to decode the bitstream of FPGAs from Xilinx Corporation,and then an analysis program is developed to parse the netlist of a specific design to get the configuration state of occupied programmable logic and routings.After that,an SEU propagation rule is established according to the resource type to identify critical logic nodes and paths,which could destroy the circuit topological structure.The decoded relationship is stored in a database.The database is queried to get the sensitive bits of a specific design.The result can be used to represent the vulnerability of the system and predict the on orbit system failure rate.The analysis tool was validated through fault injection and accelerator irradiation experiment.     

New encoding/decoding methods for designing fault-tolerant matrixoperations

Algorithm-based fault tolerance (ABFT) can provide a low-cost error protection for array processors and multiprocessor systems. Several ABFT techniques (weighted check-sum) have been proposed to design fault-tolerant matrix operations. In these schemes, encoding/decoding uses either multiplications or divisions so that overhead is high. In this paper, new encoding/decoding methods are proposed for designing fault-tolerant matrix operations. The unique feature of these new methods is that only additions and subtractions are used in encoding/decoding. In this paper, new algorithms are proposed to construct error detecting/correcting codes with the minimum Hamming distance 3 and 4. We will show that the overhead introduced due to the incorporation of fault tolerance is drastically reduced by using these new coding schemes     

PMSS: A programmable memory system and scheduler for complex memory patterns

HPC industry demands more computing units on FPGAs, to enhance the performance by using task/data parallelism. FPGAs can provide its ultimate performance on certain kernels by customizing the hardware for the applications. However, applications are getting more complex, with multiple kernels and complex data arrangements, generating overhead while scheduling/managing system resources. Due to this reason all classes of multi threaded machines–minicomputer to supercomputer–require to have efficient hardware scheduler and memory manager that improves the effective bandwidth and latency of the DRAM main memory. This architecture could be a very competitive choice for supercomputing systems that meets the demand of parallelism for HPC benchmarks. In this article, we proposed a Programmable Memory System and Scheduler (PMSS), which provides high speed complex data access pattern to the multi threaded architecture. This proposed PMSS system is implemented and tested on a Xilinx ML505 evaluation FPGA board. The performance of the system is compared with a microprocessor based system that has been integrated with the Xilkernel operating system. Results show that the modified PMSS based multi-accelerator system consumes 50% less hardware resources, 32% less on-chip power and achieves approximately a 19x speedup compared to the MicroBlaze based system.     

基于比特承诺的计算安全量子密码协议

比特承诺是重要的密码学元素,在复杂密码协议设计（如：零知识证明）中扮演着重要角色．Mayers,Lo和Chau分别独立证明了所有无条件安全的量子比特承诺方案都是不安全的,即著名的Mayers-Lo-Chau不可行定理．但这并不排除存在计算安全的量子比特承诺．2000年,Dumais等人给出了一个基于计算假设的量子单向置换可以用于构造计算安全的比特承诺方案．利用纠错码的方法,把量子比特承诺扩展成量子多比特承诺方案,并证明了所给方案的隐蔽性质和约束性质．以比特承诺方案为基础,给出了量子数字签名和量子加密认证方案的设计方法,并给出了协议的安全性证明．     

Extended overlay architectures for heterogeneous FPGA cluster management

This paper proposes a novel approach for the hardware virtualization of FPGA resources, based on overlay architectures. Overlays are reconfigurable architectures synthesized on top of commercial-of-the-shelf (COTS) FPGAs. They have demonstrated to improve portability, speed up reconfiguration, and promote resource abstraction hence durability. This work demonstrates how slightly extending the architecture overlaying on top of COTS FPGAs can bring novel features for sake of improved management of hardware tasks, and ensure the binary compatibility among heterogeneous FPGAs. This comes along with a deployment platform and a software stack offering an operating system service. As a result, the platform is capable of node-to-node a hardware application live migration, while operating a cluster of heterogeneous FPGAs. Besides, the proposed software stack ensures backward compatibility when introducing a new overlay architecture. This paper also introduces accurate cost models for the early estimation of the reconfiguration time overhead. This approach that has been demonstrated in DASIP international conference is evaluated in this paper on both the Xilinx Artix-7 and Altera Cyclone V C9 FPGAs.     

Soft error susceptibility analysis methodology of HLS designs in SRAM-based FPGAs

SRAM-based FPGAs are attractive to critical applications due to their reconfiguration capability, which allows the design to be adapted on the field under different upset rate environments. High level Synthesis (HLS) is a powerful method to explore different design architectures in FPGAs. In this paper, the HLS tool from Xilinx is used to generate different design architectures and then analyze the probability of errors in those architectures. Two different case studies scenarios are investigated. First, it is evaluated the influence of control flow and pipeline architectures combined with the use of specialized DSP blocks in the FPGA. The number of errors classified as silent data corruption and timeout according to the architectures and DSP blocks usage is analyzed. Moreover, more possibilities of HLS designs are explored such as data organization, aggressive pipeline insertion and the implementation of the algorithm in a soft processor like the Microblaze from Xilinx. These architectures are strongly optimized in performance and the least susceptible design under soft errors is investigated. All case-study designs are evaluated in a 28 nm SRAM-based FPGA under fault injection. The dynamic cross section, soft error rate and mean work between failures are calculated based on the experimental results. The proposed characterization method can be used to guide designers to select better architectures concerning the susceptibility to upsets and performance efficiency.     

高基Montgomery模乘阵列结构设计与实现

提出了两种高基Montgomery模乘线性阵列结构。两种线性阵列结构分别利用两种不同的并行化开发方法，沿不同的循环维度进行任务分配和调度，都能够充分开发算法的流水线并行。在Xilinx XC5VLX330 FPGA上实现了两种256位宽、基为216的模乘阵列结构。实验结果表明，两种结构具有84个时钟周期的延迟，吞吐率分别为1/17和1/21，与相关结构相比吞吐率更高。两种结构在性能和实现代价间能够达到合理平衡。     

一种基于线性反馈移位寄存器的轻量级强PUF 设计

物理不可克隆函数(PUF),是一种新型硬件安全原语,可以用FPGA 和ASIC 实现, 避免芯片被过度制造和非法克隆。PUF 可以用于安全密钥生成和芯片认证,强PUF 是其中一种 重要的分类,强PUF 具有极大的CRP 空间,适用于设备实体的安全认证。经典的以仲裁器PUF 为代表的强PUF 设计面积开销大,唯一性不够理想,难以在一些资源集约的场景,如嵌入式系 统和物联网(IoT)设备中应用。为了减小硬件开销,提出了一种新型轻量级强PUF 设计,该设计 利用线性反馈移位寄存器对弱PUF 的输出响应进行混淆以获得大量的输出响应,结构简单,易 于实现。在28 nm 的FPGA 上实现并评估了该PUF 设计。实验结果表明,该PUF 的随机性为 49.8%,唯一性为50.25%,硬件开销很小。     

Dynamic reconfiguration architectures for multi-context FPGAs

Field-programmable gate arrays (FPGAs) are being integrated with processors on the same motherboard or even chip in order to achieve flexible high-performance computing, and this may become main stream in chip multi-core architectures. However, the expensive FPGA area is often used inefficiently, with much of the logic idle at any given time. This work, motivated by the Dynamic-Link Library (DLL) concept in software, explores the possibility of “hardware DLLs” by finding ways for fast dynamic incremental reconfiguration of FPGAs. So doing would, among other things, enable same-function replication at any given time, with functions changing quickly over time, thereby enabling efficient exploitation of data parallelism at no additional hardware cost.We present two new multi-context FPGA architectures based on two different configuration storage architectures: local and centralized. Problems such as configuration storage and reconfiguration (time, power and space) overhead are considered. Well known area and power models are used in evaluating various approaches and in order to provide guidelines for matching architectures to target applications. Lastly, we provide insights into resulting scheduling issues. Our findings provide the foundation and “rules of the game” for subsequent development of reconfiguration schedulers and execution environments.     

Hardware–software optimizations of reconfigurable multi-core processors for floating-point computations of large sparse matrices

State-of-the-art field-programmable gate array (FPGA) technologies have provided exciting opportunities to develop more flexible, less expensive, and better performance floating-point computing platforms for embedded systems. To better harness the full power of FPGAs and to bring FPGAs to more system designers, we investigate unique advantages and optimization opportunities in both software and hardware offered by multi-core processors on a programmable chip (MPoPCs). In this paper, we present our hardware customization and software dynamic scheduling solutions for LU factorization of large sparse matrices on in-house developed MPoPCs. Theoretical analysis is provided to guide the design. Implementation results on an Altera Stratix III FPGA for five benchmark matrices of size up to 7,917 × 7,917 are presented. Our hardware customization alone can reduce the execution time by up to 17.22 %. The integrated hardware–software optimization improves the speedup by an average of 60.30 %.     

基于全局距离最优的抗污染极短纠错码设计

针对现有二维码在复杂环境中抗污染能力弱、解码速度慢的问题,提出了一种基于全局距离最优的抗污染极短纠错码。首先,构建了表征污染环境的凹凸多边形数学模型;然后,设计了采用3个编码点表示一个目标数据位的极短纠错码;最后,设计了在有限约束域内全局距离最优的编码点的编排方法,并给出了对应的解码算法。对极短纠错码的抗污染能力和识别速度进行了仿真评估,并与经典的BCH码进行了对比。结果表明,当目标数据长度为18、编码点数为63时,极短纠错码在同等污染环境中识别准确率接近BCH码,而解码速度是BCH码的130倍。所提编码还具有结构简洁明确、编码点数适应能力强、易于标准化推广应用等显著优点。     

Fault diagnosis architecture for SKINNY family of block ciphers

Cryptographic hardware and software applications are prone to various attacks either from the environments or from the attacker to gain the secret key. Resource-constrained devices use lightweight cryptographic algorithms to achieve a high level of security. It's always a trade-off between efficient resource utilization and level of security. Out of different attacks, in recent years, fault injection attacks is well matured. It becomes imperative to choose the best and efficient fault diagnosis schemes for lightweight cryptography. In this paper, we propose novel Concurrent error detection (CED), i.e., recomputing with inverted operands (REIO) method for SKINNY Family of Block Ciphers to increase the reliability. The proposed fault detection technique for SKINNY round-based pipelined architecture is adapted. The result shows that the throughput overhead of the SKINNY remains within 2.5% variance for the proposed novel fault detection with a pipelined technique, a maximum of 10% area overhead. We have implemented the proposed fault detection scheme using Xilinx FPGA. Best to our knowledge, there is no CED based fault detection technique proposed in the literature for the SKINNY family of block ciphers. The implementation results show that the proposed scheme is more effective and well suited for resource-constrained environments.     

Online scheduling and placement of hardware tasks with multiple variants on dynamically reconfigurable field-programmable gate arrays

Hardware task scheduling and placement at runtime plays a crucial role in achieving better system performance by exploring dynamically reconfigurable Field-Programmable Gate Arrays (FPGAs). Although a number of online algorithms have been proposed in the literature, no strategy has been engaged in efficient usage of reconfigurable resources by orchestrating multiple hardware versions of tasks. By exploring this flexibility, on one hand, the algorithms can be potentially stronger in performance; however, on the other hand, they can suffer much more runtime overhead in selecting dynamically the best suitable variant on-the-fly based on its runtime conditions imposed by its runtime constraints. In this work, we propose a fast efficient online task scheduling and placement algorithm by incorporating multiple selectable hardware implementations for each hardware request; the selections reflect trade-offs between the required reconfigurable resources and the task runtime performance. Experimental studies conclusively reveal the superiority of the proposed algorithm in terms of not only scheduling and placement quality but also faster runtime decisions over rigid approaches.     

A hybrid design-time/run-time scheduling flow to minimise the reconfiguration overhead of FPGAs

Current multimedia applications are characterized by highly dynamic and non-deterministic behaviour as well as high-performance requirements. Potentially, partially reconfigurable fine-grain configurable architectures like FPGAs can be reconfigured at run-time to match the dynamic behaviour. However, the lack of programming support for dynamic task placement as well as the large configuration overhead has prevented their use for highly dynamic applications. To cope with these two problems, we have adopted an FPGA model with specific support for task allocation. On top of this model, we have applied an existing hybrid design-time/run-time scheduling flow initially developed for multiprocessor systems. Finally, we have extended this flow with specific modules that greatly reduce the reconfiguration overhead making it affordable for current multimedia applications.     

A novel concurrent error detection scheme for FFT networks

The algorithm-based fault tolerance techniques have been proposed to obtain reliable results at very low hardware overhead. Even though 100% fault coverage can be theoretically obtained by using these techniques, the system performance, i.e., fault coverage and throughput, can be drastically reduced due to many practical problems, e.g., round-off errors. A novel algorithm-based fault tolerance scheme is proposed for fast Fourier transform (FFT) networks. It is shown that the proposed scheme achieves 100% fault coverage theoretically. An accurate measure of the fault coverage for FFT networks is provided by taking the round-off error into account. The proposed scheme is shown to provide concurrent error detection capability to FFT networks with low hardware overhead, high throughput, and high fault coverage     

Deterministic bit-stream digital neurons

In this paper, we present the design of a deterministic bit-stream neuron, which makes use of the memory rich architecture of fine-grained field-programmable gate arrays (FPGAs). It is shown that deterministic bit streams provide the same accuracy as much longer stochastic bit streams. As these bit streams are processed serially, this allows neurons to be implemented that are much faster than those that utilize stochastic logic. Furthermore, due to the memory rich architecture of fine-grained FPGAs, these neurons still require only a small amount of logic to implement. The design presented here has been implemented on a Virtex FPGA, which allows a very regular layout facilitating efficient usage of space. This allows for the construction of neural networks large enough to solve complex tasks at a speed comparable to that provided by commercially available neural-network hardware.     

A novel BRAM content accessing and processing method based on FPGA configuration bitstream

This paper presents a new approach to manage data content of memories implemented in FPGAs through the configuration bitstream. The proposed approach is able to read and write the data content from Block RAMs (BRAMs) in FPGA based designs by reading and processing the information stored in the bitstream. Thanks to this method it is possible to extract, load, copy or compare the information of BRAMs without neither resource overhead nor performance penalty in the design. It can also be applied to existing designs without the need of re-synthesizing. Due to its advantages it becomes an interesting tool to carry out several applications, such as error detection and recovery or fault injection. It also opens the doors to the design of cutting-edge applications. The approach has been implemented in a Xilinx ZYNQ System-on-Chip (SoC) device, which combines an FPGA and an ARM9 microprocessor. The access to the configuration bitstream has been performed using the ZYNQ’s Processor Configuration Access Port (PCAP). Nevertheless, the flow presented in this article can be adapted to devices from other Xilinx families or vendors. The proposed approach has been fully tested and compared with specifically designed memory controllers. The results obtained in the experimental tests confirm that the proposed approach works properly without increasing the resource overhead but at a penalty in terms of processing time.