SpExSim: assessing kernel suitability for C-based high-level hardware synthesis

We present SpExSim, a software tool for quickly surveying legacy code bases for kernels that could be accelerated by FPGA-based compute units. We specifically aim for low development effort by considering the use of C-based high-level hardware synthesis, instead of complex manual hardware designs. SpExSim not only exploits the spatially distributed model of computation commonly used on FPGAs, but can also model the effect of two different microarchitectures commonly used in C-to-hardware compilers, including pipelined architectures with modulo scheduling. The estimations have been validated against actual hardware generated by two current HLS tools.

     

Lower Bound Estimation of Hardware Resources for Scheduling in High-Level Synthesis

In high-level synthesis of VLSI circuits,good lower bound prediction can efficiently narrow down the large space of possible designs.Previous approaches predict the lower bound by relaxing or even ignoring the precedence constraints of the data flow graph (DFG),and result in inaccuracy of the lower bound.The loop folding and conditional branch were also not considered,In this paper,a new stepwise refinement algorithm is proposed.which takes consideration of precedence constraints of the DFG to estimate the lower bound of hardware resources under time constratints,Processing techniques to handle multi-cycle,chaining,pipelining,as well as loop folding and mutual exclusion among conditional branches are also incorporated in the algorithm.Experimental results show that the algorithm can produce a very tight and close to optimal lower bound in reasonable computation time.     

TCP flow control technique for an interworking interface: hardware implementation

Current TCP flow control depends on packet losses to find the workload that a network can support. A variety of situations, including lossy wireless networks, asymmetric networks and web traffic workload, violates many of the assumptions made by TCP, causing degraded end-to-end performances. To improve the performance of TCP over heterogeneous networks (Ethernet and ATM interconnection), we propose a new technique, which we call Vegas–Snoop+, based on Vegas and Snoop protocols. Two modified service elements take part on the Vegas–Snoop+ technique. First, Vegas service element manages the connection parameters to achieve better throughput. Second, Snoop service element isolates the Ethernet senders from the characteristics of the ATM link. The objective in this paper is to win from advantages of Vegas and Snoop protocols, as well as to search an interconnection interface for networks interoperability. Actually, the development of two new integrated circuits (the BCM5680 (switch) and the BCM5401 (PHY)) orientate researchers to implement, at higher layer of the OSI model, flow control mechanisms to ensure reliability. Vegas–Snoop+ is an implementation of TCP, which gives in this way a solution for traffic management and congestion control improving good throughput with more reliability.     

一种基于硬件的大规模哈希流表设计与实现

基于流的报文处理是防火墙、入侵检测等网络安全应用的重要组成功能,其中流表是流处理技术的关键数据结构,流表的规模及访问性能直接影响到流处理的能力和速度。着眼于高速网络下大规模流表的硬件实现,设计了一种基于硬件的千万级哈希流表查找架构,并在FPGA平台上进行了实现和测试。该方案在保证访存效率的同时很好地解决了冲突的难题,利用有限的存储资源,满足了高达4 900万项的流表查找需求,测试能够实现92Mdesc/s的表查找速度,支持约220Gbps高速以太网的处理能力。     

Automatic generation of MPEG test streams from high-level grammars

This paper describes a technique to generate complex, moving picture experts group (MPEG) data streams containing packets which range through a selected set of variants, as allowed by the grammar of the packet stream. The Prolog logic programming language has been used, whose declarative power allows data generation almost directly from the grammar, i.e. without the need for explicitly programming a grammar traversal mechanism as would be the case with an imperative language. A reasonably declarative style of grammar and variation definition is achieved, and at the same time, a reasonably efficient generation process. The basic idea is to use a declarative fragment of Prolog for the grammar, but to use imperative features of Prolog for matters like packet enumeration and packet payload generation. Generation of test data from grammars is not new, nor is the use of Prolog programs for generation of test data, but as far as we know, the combination of both has not reported on in the literature, nor its application to MPEG demultiplexers/decoders.     

Automatic synthesis of communication controller hardware fromprotocol specifications

Controllers for serial protocols are control-oriented designs that include complex state machines. Manually designing protocol controllers is thus tedious, error prone, and time-consuming. We present a new methodology for the efficient design of communication controller hardware suited for (but not limited to) complex, bit-serial protocols. Our methodology synthesizes controller hardware from a formal high-level specification of the protocol. In this approach, a single run of the synthesis algorithm synthesizes a complete communication architecture from a single protocol specification. The method not only reduces modeling effort but also ensures that both the interacting transaction producer and consumer controllers conform to the initial protocol specification     

Algorithms for high-level synthesis

Synthesis algorithms that offer a technique for scheduling operations and allocating registers and buses in light of both timing constraints and available hardware resources are presented. They enhance current scheduling techniques by using a global priority function that minimizes storage, interconnections, and functional unit cost. Algorithms for allocating registers and buses minimize storage and interconnection costs and take into account the interdependence of both tasks. The algorithms are also applicable to more than one method of synthesis; although first implemented in the HAL system, they have since been integrated into more specialized high-level synthesis systems     

基于支持向量机的滤波器设计与硬件实现

针对传统有限脉冲响应(FIR)滤波器设计方法和神经网络设计方法的不足,在改进使用支持向量机(SVM)设计FIR滤波器方法的基础上,提出了SVM设计FIR滤波器的硬件实现方法.使用理想滤波器的幅值响应训练SVM,得到训练参数,据此构建基于SVM的FIR滤波器的嵌入式系统.软件实现FIR滤波器的训练部分,硬件实现FIR滤波器的测试部分.单次判定测试向量的时间约为3500 ns,滤波准确率可达到98.41%.设计的滤波器具有良好的幅频特性,边界控制精确,逼近理想滤波器.     

Automatic generation of process flow diagrams

An algorithm which automates the generation of process flow diagrams for distributed programs has been developed. The algorithm maps a graph specification to a graph diagram. The implementation of a graphics monitor uses process flow diagrams to monitor execution of distributed programs on an experimental multiprocessor system. Process states are superimposed onto process flow diagrams to enhance visualization of the execution sequence. Techniques of clustering and unclustering processes are also described.     

On hardware synthesis and implementation of PLC programs in FPGAs

Many processes require controllers with an instant response (e.g. motor control, CNC machines). A high-performance PLC can be constructed with use of programmable logic devices. A lack of custom synthesis tools disables the use of standard languages widely accepted by automation designers. The paper presents the systematic process of a PLC program synthesis to hardware structure. An input PLC program is given according to the IEC61131-3 standard. The synthesis process has been developed for implementation of a program described with the LD and SFC languages. The essential idea of synthesis process is obtaining a massively parallel operating hardware structure that significantly reduces response processing time. The PLC program is translated into originally developed dedicated graph structure that enables a wide range of optimizations. In the next step, it is mapped into a hardware structure. In order to reduce resource requirements, a strategy with resource sharing is shown, which is an original extension of general mapping concepts. Modern FPGAs are equipped with arithmetic cores dedicated for signal processing, inspiring the development of the original DSP48 block mapping strategy. It attempts to utilize all features of the block in the pipelined calculation model. The considerations are summarized with the implementation result compared against standard PLC implementation, a mutual comparison of general hardware mapping, and with the use of DSP48 units.     

An investigation of software describing methods to design dual background scrolling hardware in high-level synthesis

Artificial Life and Robotics - We are developing a game programing library which can be converted to hardware modules by high-level synthesis, HLS technology to realize high-performance and...     

适合AES算法硬件实现的新S盒

为了提高AES算法在硬件平台上的实现性能,通过对AES算法S盒构造原理进行分析,构造了一个新S盒。与AES算法的S盒相比,新S盒在硬件实现时将使用更少的硬件资源并具有更快的运行速度,因而更适合在低档硬件上实现。同时,分析并证明了新S盒不会影响修改后的AES算法的强度。     

DCT硬件实现的通用性探究

在分析了DCT的原理以及采用蝶形快速算法的实现方法的基础上,提出一种可以实现不同尺寸模块调用的方法.为了达到减少硬件实现上复杂度的目的,DCT处理器采用模块化的思想,将系统划分为不同的功能模块,这样在提高硬件电路通用性的同时增强了DCT在实际应用中的灵活性.使用Verilog HDL硬件描述语言进行参数化RTL级描述,在SUSE Linux环境下的NC-Launch软件上进行仿真验证.实验验证了所设计模块功能上的正确性.在应用中,本设计能提高硬件电路的通用性和DCT的灵活性.     

Post-quantum signature schemes for efficient hardware implementation

Post-quantum cryptosystems have attracted a great interest, from researchers, latest. This work introduces two new forms of the hidden discrete logarithm problem and three new post-quantum signature schemes. The finite non-commutative associative algebras of two types are used as the algebraic support of the proposed cryptoschemes: i) containing a global two-sided unit and ii) containing a large set of global left-sided units. The illustrated FPGA implementation results, show the efficiency of the proposed cryptographic schemes, in hardware approaches. Detailed comparisons, with other security hardware implementations, are also presented.     

基于WMI硬件ID激活策略的研究与实现

用客户端PC机器上所有硬件作为客户端唯一标识,而不是某一个硬件,而取得PC机器上所有硬件的ID必须要用到Windows管理规范(WMI)技术.有些硬件本身就没有ID标识,而有些硬件ID的重复率很高,为了解决这个问题,需要采用权值的概念,对于不同的硬件,它所对应的权值是不一样的.为了保护PC机的ID,需要用Hash算法得到每个硬件ID的Hash值,用这些Hash值作为客户端的标识;把客户端所有硬件ID的Hash值组包发送到服务器,这样服务器端就得到了客户端的信息.     

基于FPGA的FLAC音频硬解码的设计与实现

针对高保真FLAC音频播放系统中软件解码效率低下、占用系统资源大的问题,提出一种基于FPGA的FLAC音频硬解码的设计方案。分析了FLAC音频基本编解码原理,并详细介绍了基于现场可编程门阵列(FPGA)器件的FLAC解码器各模块的设计思想和实现。利用Verilog语言在Quartus II的开发环境中进行设计输入与仿真验证。实验测试结果表明,该FLAC解码器设计灵活、工作稳定可靠、解码效率高,可作为IP核应用于不同SoC的无损音频播放系统中。