Design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells

Emerging non-volatile memories (e.g. STT-MRAM, OxRRAM and CBRAM) based on resistive switching are under intense research and development investigation by both academics and industries. They provide high performance such as fast write/read speed, low power and good endurance (e.g. >10¹²), and could be used as both computing and storage memories beyond flash memories. However the conventional access architecture based on 1 transistor + 1 memory cell limits its storage density as the selection transistor should be large enough to ensure enough current for the switching operation. This paper presents the design and analysis of crossbar architecture based on complementary resistive switching non-volatile memory cells with a particular focus on reliability and power performance investigation. This architecture allows fewer selection transistors, and minimum contacts between memory cells and CMOS control circuits. The complementary cell and parallel data sensing mitigate the impact of sneak currents in the crossbar architecture and provide fast data access for computing purpose. We perform transient and statistical simulations based on two memory technologies: STT-MRAM and OxRRAM to validate the functionality of this design by using CMOS 40 nm design kit and memory compact models, which were developed based on relative physics and experimental parameters.     

Coverage Optimization for Defect-Tolerance Logic Mapping on Nanoelectronic Crossbar Architectures

Emerging nano-devices with the corresponding nano-architectures are expected to supplement or even replace conventional lithography-based CMOS integrated circuits, while, they are also facing the serious challenge of high defect rates. In this paper, a new weighted coverage is defined as one of the most important evaluation criteria of various defect- tolerance logic mapping algorithms for nanoelectronic crossbar architectures functional design. This new criterion is proved by experiments that it can calculate the number of crossbar modules required by the given logic function more accurately than the previous one presented by Yellambalase et al. Based on the new criterion, a new effective mapping algorithm based on genetic algorithm (GA) is proposed. Compared with the state-of-the-art greedy mapping algorithm, the proposed algorithm shows pretty good effectiveness and robustness in experiments on testing problems of various scales and defect rates, and superior performances are observed on problems of large scales and high defect rates.     

Area-Delay-Energy aware SRAM memory cell and M × N parallel read/write memory array design for quantum dot cellular automata

Quantum dot Cellular Automata (QCA) is an emerging nanotechnology, potentially suitable to replace the popular technologies like Complementary Metal Oxide Semiconductor (CMOS) technology. The evolution of QCA has become prominent due to high operating frequency, nanoscale device and zero current low power nanotechnology. However, the Area-Delay-Energy aware QCA logic circuit design remains a prime concern in this post CMOS technology. In this work the primary attention is given to build efficient QCA circuits. The motivation of this work is to propose Efficient VLSI design in terms of Area, Delay, Power and PDP (Power delay product). Different methodologies are reported to design a combinational and sequential circuit in QCA technology. An extensive focus is given in designing of 3 different QCA based Area-Delay-Energy aware SRAM memory cells, parallel read/write M × N SRAM memory array and peripherals like decoder and multiplexer. Since appropriate signal distribution network (SDN) is an essential aspect to deign QCA circuit, it has also been reported a delay aware signal distribution methodology applicable for any type of QCA logic circuit design. The significant results of this research finding are expressed in terms of Area-Delay-Energy dissipation tradeoff. When compared with respective to the state of art, the performance metric of proposed QCA based memory cells are excelled, on an average 40% reduction in area, 33% and 22% drop in delay and energy dissipation respectively are achieved for proposed three different memory cell design.     

基于互补电阻开关的忆阻乘法器设计

现有的忆阻算术逻辑多采用单个忆阻器作为存储单元,在忆阻交叉阵列中易受到漏电流以及设计逻辑电路时逻辑综合复杂度高的影响,导致当前乘法器设计中串行化加法操作的延时和面积开销增加。互补电阻开关具有可重构逻辑电路的运算速度和抑制忆阻交叉阵列中漏电流的性能,是实现忆阻算术逻辑的关键器件。提出一种弱进位依赖的忆阻乘法器。为提升忆阻器的逻辑性能,基于互补电阻开关电路结构,设计两种加法器的优化方案,简化操作步骤。在此基础上,通过改进传统的乘法实现方式,并对进位数据进行拆解,降低运算过程中进位数据之间的依赖性,实现并行化的加法运算。将设计的乘法器映射到混合CMOS/crossbar结构中,乘法计算性能得到大幅提高。在Spice仿真环境下验证所提乘法器的可行性。仿真实验结果表明,与现有的乘法器相比,所提乘法器的延时开销从O(n²)降低为线性级别,同时面积开销降低约70%。     

Low-cost testing of high-density logic components

The evolution of a testing method and architecture of a logic-device tester to be used for the next generation of IBM's high-density CMOS ASIC (application-specific integrated circuit) logic components is described. The tester's design is based on the architecture of an existing IBM memory tester rather than on a conventional logic-tester design. The testing strategy calls for boundary-scan in each component design, built-in self-test logic within embedded memory arrays, and the use of weighted random-pattern logic testing. The development of the tester hardware is discussed, and capital costs of the new tester are compared with those of other approaches     

A novel adaptive learning algorithm for low-dimensional feature space using memristor-crossbar implementation and on-chip training

Proposing an efficient algorithm with an appropriate hardware implementation has always been an interesting and a rather challenging field of research in Artificial Intelligence (AI). Fuzzy logic is one of the techniques that can be used for accurate and high-speed modeling as well as controlling complex and nonlinear systems. The “defuzzification” process during the test phase as well as the repetitive processes in order to find the optimal parameters during the training phase, lead to some serious limitations in real-time applications and hardware implementation of these algorithms. The proposed algorithm employs Ink Drop Spread (IDS) concept to mimic the functionality of human brain. In this algorithm, learning is based on the distance between training data and the “learning plane”. Unlike previous algorithms, the new one does not need to partition nor the input space neither the calculation of IDS plane features. Besides, the output is obtained without using the optimization methods. The proposed algorithm is a numerical foundation that does not encounter a processing problem and lack of memory in dealing with different datasets consisting of a large number of samples. This algorithm can be efficiently implemented on memristor crossbar/CMOS hardware platform in terms of area and speed. This hardware has the ability to learn and adapt to the environment regardless of a host system (on-chip learning capability). Finally, to verify the performance of the proposed algorithm, it has been compared to ALM, RBF and PNN algorithms which have a similar functionality.     

Building an FoC Using Large, Buffered Crossbar Cores

The latest improvements in CMOS technologies have eliminated buffered crossbar memory requirements. Combined with a novel microarchitecture approach, these new technologies allow for implementation of a combined input-crosspoint queuing (CICQ), single-chip 32 × 32 switch as the core for a future fabric on a chip (FoC). This switch operates directly on variable-size packets, reducing overall data path complexity and increasing effective bandwidth     

基于电流信息的CMOS SRAM存储单元故障测试

针对深亚微米技术,提出了差分静态电流技术和动态电流技术相结合的方法对CMOS SRAM存储单元进行故障诊断,针对该方法改进了0-1算法。改进的0-1算法与传统的March算法相比,明显降低了测试开销。以四单元存储器为诊断实例,针对桥接故障、开路故障与耦合故障,实现了100%故障诊断覆盖率。实验结果证明了新方法具有故障覆盖率高的特点,能够诊断传统逻辑测试法难以探测的部分故障。     

Physical synthesis of quantum circuits using templates

Similar to traditional CMOS circuits, quantum circuit design flow is divided into two main processes: logic synthesis and physical design. Addressing the limitations imposed on optimization of the quantum circuit metrics because of no information sharing between logic synthesis and physical design processes, the concept of “physical synthesis” was introduced for quantum circuit flow, and a few techniques were proposed for it. Following that concept, in this paper a new approach for physical synthesis inspired by template matching idea in quantum logic synthesis is proposed to improve the latency of quantum circuits. Experiments show that by using template matching as a physical synthesis approach, the latency of quantum circuits can be improved by more than 23.55 % on average.     

Design for innovation – A methodology to engineer the innovation diffusion into the development process

In its hyper-inflated usage, innovation simply means “something new”, and is applied to any technical novelty. In its true meaning, innovating means designing something that will not only work under a technical point of view, but will also make business sense. “Design for Innovation” means considering that design cannot simply focus on a narrow meaning of “product use”, because this could severely limit the diffusion of innovative products. The paper proposes an original model for representing what we call “beyond-use situations” and the influences among the actors involved in the innovation diffusion process.Taking inspiration from social influence network models and from the Multi-issue Actor Strategy Analysis Model (MASAM), the paper presents an operational methodology to assess the influence of different actors on the decision to adopt a new product. In turn, such methodology should support design teams to conceive novel solutions more likely to become factual innovations. The paper also describes a computer-implementable technique, loosely derived from Quality Function Deployment, to practically apply the proposed methodology. An industrial case study from the medical-care sector illustrates its logic and operational steps.     

Design of BCD adder with five input majority gate for QCA

In the digital world BCD numbers play a pivotal role in constituting decimal numbers. New different technologies are emerging in order to obtain low area/power/delay factors to replace the CMOS technology. One such technology is quantum cellular automata (QCA) realization, through which many arithmetic circuits can be designed. This paper deals with the implementation of BCD adder with 5 input majority gates for QCA. The 3 input majority gate and an inverter are basic elements of QCA. In this project amalgamation of majority gates with 3 and 5 inputs are used instead of implementing the entire circuit using 3 input majority gate in the BCD i.e. mainly comprised by partly consumed gates and entirely consumed gates. The proposed is designed and functional verification is done by Verilog HDL and Modelsim version 10.4a. The proposed design has been verified and the delay of existing and proposed design is analysed using Xilinx tool. The numbers of partly consumed and entirely consumed gates are less when compared to the existing method of implementation. The delay is reduced compared to the existing system which shows the improvement of 9.84%. The drawback of crossovers that leads the difficulty in implementation and reduces the efficiency of the circuit is reduced in the proposed implementation.     

Architecture of a Terabit Free-Space Intelligent Optical Backplane

Optical technologies can support thousands of high bandwidth optical channels to/from a single CMOS integrated circuit, and can thus allow for the construction of novel bandwidth-intensive computing architectures which are no longer constrained by conventional electronic wiring limitations. In this paper, the architecture of a dynamically reconfigurableIntelligent Optical Backplaneis described. The backplane consists of a large number of parallel optical channels (typically 1000–10,000 bits) spaced a few hundred micrometers apart. The optical channels are arranged into upstream and downstream rings, where the channel access protocols are implemented by “smart pixel arrays.” The architecture exploits thebandwith advantageof the optical domain and can be dynamically reconfigured to embed conventional interconnection networks, including multiple busses, rings, and meshes. Unlike all-optical and passive optical systems, the proposed backplane is intelligent and can support communication primitives used in shared memory multiprocessing, including broadcasting, multicasting, acknowledgment, flow and error-control, buffering, shared memory caching, and synchronization. The backplane is also manufacturable using existing optoelectronic technologies. A second generation backplane supporting a distributed shared memory multi-processor is under development.     

Heterogeneous graphene–CMOS ternary content addressable memory

Leveraging nanotechnology for computing opens up exciting new avenues for breakthroughs. For example, graphene is an emerging nanoscale material and is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability. Recently, a new graphene nanoribbon crossbar (xGNR) device was proposed which exhibits negative differential resistance (NDR). In this paper we propose a novel graphene nanoribbon tunneling ternary content addressable memory (GNTCAM) enabled by xGNR device, featuring heterogeneous integration with CMOS transistors and routing. Benchmarking with respect to 16nm CMOS TCAM (which uses two binary SRAMs to store ternary information) shows that GNTCAM is up to 1.82× denser, up to 9.42× more power-efficient during stand-by, and has up to 1.6× faster performance during match operation. Thus, GNTCAM has the potential to realize low-power high-density nanoscale TCAMs. Further improvements may be possible by using graphene more extensively, as graphene transistors become available in future.     

User-programmable gate arrays: design methodology and development systems

Unlike conventional mask-programmed gate arrays, the logic, I/O functions, 7 and interconnections of Xilinx-programmable gate arrays, logic cell arrays (LCAs), are fully user programmable. The functions implemented in an LCA are determined by a configuration program that is loaded during system initialization, much like a programmable microprocessor peripheral. Powerful development tools allow the designer to progress easily from design conception to the generation of the LCA configuration programs. The basic design methodology involves three main steps: design entry, design implementation, and design verification.     

Designing with programmable logic arrays

Programmable logic arrays (PLAs) are characterized by the ability to replace discrete logic components and their equivalent functions in a variety of system designs. With the advent of new technologies and computer software tools such as Amaze, the exercise of designing with PLAs has been simplified. This paper provides a tutorial overview of various aspects of designing with PLAs, and discusses their uses and basic variations to their structures. A design example involving a single-board computer is presented; the control logic in this design can easily be adapted to other single-board computers.     

A class of highly scalable optical crossbar-connectedinterconnection networks (SOCNs) for parallel computing systems

A class of highly scalable interconnect topologies called the Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) is proposed. This proposed class of networks combines the use of tunable Vertical Cavity Surface Emitting Lasers (VCSEL's), Wavelength Division Multiplexing (WDM) and a scalable, hierarchical network architecture to implement large-scale optical crossbar based networks. A free-space and optical waveguide-based crossbar interconnect utilizing tunable VCSEL arrays is proposed for interconnecting processor elements within a local cluster. A similar WDM optical crossbar using optical fibers is proposed for implementing intercluster crossbar links. The combination of the two technologies produces large-scale optical fan-out switches that could be used to implement relatively low cost, large scale, high bandwidth, low latency, fully connected crossbar clusters supporting up to hundreds of processors. An extension of the crossbar network architecture is also proposed that implements a hybrid network architecture that is much more scalable. This could be used to connect thousands of processors in a multiprocessor configuration while maintaining a low latency and high bandwidth. Such an architecture could be very suitable for constructing relatively inexpensive, highly scalable, high bandwidth, and fault-tolerant interconnects for large-scale, massively parallel computer systems. This paper presents a thorough analysis of two example topologies, including a comparison of the two topologies to other popular networks. In addition, an overview of a proposed optical implementation and power budget is presented, along with analysis of proposed media access control protocols and corresponding optical implementation     

A new methodology for deriving the rule-base of a fuzzy logic controller with a new internal structure

In this study, a fuzzy logic controller is developed using a new methodology for designing its rule-base. This controller consists of two rule-base blocks and a logical switch in between. The rule-base blocks admit two inputs one of which is newly devised and called “normalized acceleration” and the other one is the classical “error”. The newly devised input is derived using the first and the second order derivatives of the error and it gives a relative value about the “fastness” or “slowness” of the system response. A comparative performance analysis has been made through the simulation results of the MacVicar-Whelan controller and the proposed fuzzy logic controller on a marginally stable system. The robustness and effectiveness of the new fuzzy logic controller over the typical MacVicar-Whelan controller has also been illustrated by simulations done on a system under various disturbances and time delays.     

Second thoughts on parallel processing

A variety of advanced, high-throughput “parallel” and “associative” computer architectures are discussed. In comparing the architectures we argue that it is useful to view them simply as alternative ways of increasing the amount of processing hardware relative to the amount of memory hardware. Another useful criterion is the duty cycle of the processing hardware, i.e. the proportion of the total amount of arithmetic and logical activity that is meaningful.Digital signal processing is considered as an example application. We conclude that cellular-logic-in-memory arrays are inappropriate for signal processing.     

Achieving Accurate Timing Measurements on TTL/CMOS Devices

Production TTL and CMOS timing measurements obtained between different test systems and between test systems and the bench setup often do not correlate or do not appear to be accurate even though the automatic test equipment system has subnanosecond accuracy. Errors of as much as 2 ns can occur with small-, medium-, and large-scale integration and with gate arrays using the new TTL and CMOS technologies. This represents a 100- percent error factor for these emerging products.