Effect of bottom electrodes on resistance degradation and breakdownof (Ba,Sr)TiO3 thin films

The influence of bottom electrodes (Pt, Ir, Ru) on the degradation of (Ba,Sr)TiO₃ (BST) thin films under dc stress conditions was investigated. The current-time (I-t) and current-voltage (I-V) measurement results indicated that the BST thin films deposited on Ru have faster degradation than those deposited on Pt and Ir. The degradation was considered to be caused by the deterioration of the Schottky-barrier. Under dc stress conditions, the dielectric relaxation current in the BST dielectric films probably enhances the deterioration. The breakdown time was found to be approximated by an exponential function of an electric field [t_B=α exp(-βE)] for dc stress. The value of the exponential factor β for BST deposited on Pt and Ir was about a quarter of that for BST deposited on Ru. The different value of β observed under dc stress indicates that the degradation of BST on Ru would be more serious than on Pt and Ir. The ten years lifetime of time-dependent dielectric breakdown (TDDB) studies indicate that BST on Pt, Ir and Ru have longer lifetime over ten years for operation at the voltage bias of 1 V     

A stacked capacitor technology with ECR plasma MOCVD(Ba,Sr)TiO3 and RuO2/Ru/TiN/TiSixstorage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO₃ thin films is described, The four-layer RuO₂/Ru/TiN/TiSi_x, storage node configuration allows 500°C processing and fine-patterning down to the 0.20 μm size by electron beam lithography and reactive ion etching. Good insulating (Ba_0.4Sr_0.6)TiO₃ (BST) films with an SiO₂ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1×10^{-/6 A}cm² at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 μm size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 μm² with only the 0.3 μm high-storage electrodes     

Novel capacitor process using diffusion barrier rounded by Si3N4 spacer for high density FRAM device

A novel capacitor process was successfully implemented in 4 Mb FRAM device by developing a barrier layer rounded by Si₃N₄ spacer (BRS) scheme. Using this process, it is possible to eliminate an undesired barrier etching damage, which is a major role in degrading ferroelectric properties. The novel capacitor process was generated by etching an Ir barrier layer and rounding the barrier by a Si₃N₄ spacer before preparing Pb(Zr _1-xTi_x)O₃ (PZT) films. It was observed that uniform sol-gel derived PZT films were prepared on the patterned Ir substrate by using Si₃N₄ spacer, which provides a smooth edge of the patterned cell. The contact resistance between bottom electrode and polysilicon plug after full integration was monitored below 700 Ω per contact with contact size 0.6×0.6 (μm²). Compared to the ferroelectric capacitor damaged by barrier etching, the novel Pb(Zr_1-xTi_x)O₃ (PZT) capacitor exhibited a well-saturated Q-V curve. The fully processed novel capacitor having 1.2×1.2 (μm²) effective area displayed remnant polarization of 14 (μC/cm²) at an operating voltage of 3.0 V. The BRS ferroelectric capacitor showed a reliable retention property until 100 h at 125°C. Same state retention (Qss) was stable with time up to 100 h while opposite state retention (Qos) showed a log-linear decay rate at 125°C thermal stress     

Good High-Temperature Stability of TiN/ Al2O3/WN/TiN Capacitors

For the first time, good thermal stability up to an annealing temperature of 1000degC has been demonstrated for a new TiN/Al₂O₃/WN/TiN capacitor structure. Good electrical performance has been achieved for the proposed layer structure, including a high dielectric constant of ~ 10, low leakage current of 1.2times10^-7 A/cm² at 1 V, and excellent reliability. A thin WN layer was incorporated into the metal-insulator-metal capacitor between the bottom TiN electrode and the Al₂O₃ dielectric suppressing of interfacial-layer formation at Al₂ O₃/TiN interfaces and resulting in a smoother Al₂O₃/TiN interface. This new layer structure is very attractive for deep-trench capacitor applications in DRAM technologies beyond 50 nm.     

Electrical conduction and dielectric breakdown in aluminum oxideinsulators on silicon

Leakage currents and dielectric breakdown were studied in MIS capacitors of metal-aluminum oxide-silicon. The aluminum oxide was produced by thermally oxidizing AlN at 800-1160°C under dry O₂ conditions. The AlN films were deposited by RF magnetron sputtering on p-type Si (100) substrates. Thermal oxidation produced Al ₂O₃ with a thickness and structure that depended on the process time and temperature. The MIS capacitors exhibited the charge regimes of accumulation, depletion, and inversion on the Si semiconductor surface. The best electrical properties were obtained when all of the AlN was fully oxidized to Al₂O₃ with no residual AlN. The MIS flatband voltage was near 0 V, the net oxide trapped charge density, Q_0x, was less than 10¹¹ cm ^-2, and the interface trap density, D_it, was less than 10¹¹ cm^-2 eV^-1, At an oxide electric field of 0.3 MV/cm, the leakage current density was less than 10^-7 A cm^-2, with a resistivity greater than 10 ¹² Ω-cm. The critical field for dielectric breakdown ranged from 4 to 5 MV/cm. The temperature dependence of the current versus electric field indicated that the conduction mechanism was Frenkel-Poole emission, which has the property that higher temperatures reduce the current. This may be important for the reliability of circuits operating under extreme conditions. The dielectric constant ranged from 3 to 9. The excellent electronic quality of aluminum oxide may be attractive for field effect transistor applications     

Highly reliable, high-C DRAM storage capacitors with CVD TA2O5 films on rugged polysilicon

The authors report on a highly reliable stacked storage capacitor with ultrahigh capacitance using rapid-thermal-annealed low-pressure chemical vapor deposited (LPCVD) Ta₂O₅ films (~100 Å) deposited on NH₃-nitrided rugged poly-Si electrodes. Capacitances as high as 20.4 fF/μ² (corresponding to the thinnest t_ox.eff (16.9 Å) ever reported using LPCVD-Ta₂O₅ and poly-Si technologies) have been achieved with excellent leakage current and time-dependent dielectric breakdown (TDDB) characteristics. Extensive electrical characterization over a wide temperature range (~25-300°C) shows that Ta₂O ₅ films on rugged poly-Si electrodes have a better temperature stability in dielectric leakage and breakdown compared to the films on smooth poly-Si electrodes     

Nitrogen-implanted SiC diodes using high-temperature implantation

6H-SiC diodes fabricated using high-temperature nitrogen implantation up to 1000°C are reported. Diodes were formed by RIE etching a 0.8-μm-deep mesa across the N⁺/P junction using NF₃/O₂ with an aluminum transfer mask. The junction was passivated with a deposited SiO₂ layer 0.6 μm thick. Contacts were made to N⁺ and P regions with thin nickel and aluminum layers, respectively, followed by a short anneal between 900 and 1000°C. These diodes have reverse-bias leakage at 25°C as low as 5×10^-11 A/cm² at 10 V     

Electrical characteristics of highly reliable ultrathin hafniumoxide gate dielectric

Electrical and reliability properties of ultrathin HfO₂ have been investigated. Pt electroded MOS capacitors with HfO₂ gate dielectric (physical thickness ~45-135 Å and equivalent oxide thickness ~13.5-25 Å) were fabricated. HfO₂ was deposited using reactive sputtering of a Hf target with O₂ modulation technique. The leakage current of the 45 Å HfO₂ sample was about 1×10^-4 A/cm ² at +1.0 V with a breakdown field ~8.5 MV/cm. Hysteresis was <100 mV after 500°C annealing in N₂ ambient and there was no significant frequency dispersion of capacitance (<1%/dec.). It was also found that HfO₂ exhibits negligible charge trapping and excellent TDDB characteristics with more than ten years lifetime even at V_DD=2.0 V     

High-κ Al2O3−HfTiO Nanolaminates With Less Than 0.8-nm Equivalent Oxide Thickness

High quality nanolaminate stacks consisting of five Al₂O₃-HfTiO layers with an effective dielectric constant of about 22.5 are reported. A dielectric constant for binary HfTiO thick films of about 83 was also demonstrated. The electrical characteristics of as-deposited structures and ones which were annealed in an O₂ atmosphere at up to 950 degC for 5-10 min were investigated. Two types of gate electrodes: Pt and Ti were compared. The dielectric stack which was annealed up to 500 degC exhibits a leakage current density as small as ~1times10^-4 A/cm² at an electric of field 1.5 MV/cm for a quantum-mechanical corrected equivalent oxide thickness of ~0.76 nm. These values change to ~1times10^-8 A/cm² and 1.82 nm, respectively, after annealing at 950 degC     

Effects of surface pretreatment of polysilicon electrode prior toSi3N4 deposition on the electrical characteristicsof Si3N4 dielectric films

Effects of various surface pretreatments of polysilicon electrode prior to Si₃N₄ deposition on leakage current, time-dependent dielectric breakdown (TDDB) and charge trapping characteristics of thin Si₃N₄ films deposited on rugged and smooth poly-Si are investigated. Surface pretreatments consist of different combinations of HF clean, rapid thermal H₂ -Ar clean, and rapid thermal NH₃-nitridation (RTN) and are intended to modify the surface of bottom poly-Si electrode. Results show that RTN treatments lead to lower leakage current, reduced charge trapping, and superior TDDB characteristics as compared to rapid thermal H₂-Ar clean     

Studies of yttrium oxide films prepared by RF magnetron sputtering

Films of yttrium oxide (Y₂O₃) were deposited on Si substrates from a Y₂O₃ target by RF magnetron sputtering. MIS capacitors in the form of Al and Y₂O₃ (400 Å)-Si were then fabricated. The leakage current density was about 10^-6 A/cm² at 1.3×10⁶ V/cm, and the breakdown field of the films was about 2.75×10⁶ V/cm. The dielectric constant of the sputtered Y₂O₃ was found to be about 12-12.7     

Room-Temperature Deposited Titanium Silicate Thin Films for MIM Capacitor Applications

High-k titanium silicate (i.e., TiSiO₄) thin films of various thicknesses (in the 4.5- to 160-nm range) were successfully deposited by means of a sputter deposition process at room-temperature and integrated into metal-insulator-metal (MIM) capacitors. It is shown that the TiSiO₄-based capacitors can exhibit a capacitance density as high as 30 fF/mum² while maintaining low dielectric dispersion and losses. An excellent voltage linearity was also obtained ( alpha~600 ppm/V² at 8.2 fF/mum²) together with a high dielectric constant of 16.5 and low leakage current of about 10 nA/cm² at 1 MV/cm. Our results thus show that TiSiO₄ films constitute a very promising approach for the achievement of high performance MIM capacitors     

Low-temperature fabrication of amorphous BaTiO3thin-film bypass capacitors

Amorphous BaTiO₃ thin-film capacitors suitable for integration into a multichip module packaging process were fabricated. The multilayer capacitor structure consisted of an adhesion layer (TiO _xN_y or Ti), a bottom electrode (Cu), a dielectric (amorphous BaTiO₃), and a top electrode (Cu). A 3000-Å amorphous BaTiO₃ film was deposited onto the electrode by the reactive partially ionized beam (RPIB) technique at near room temperature. After a 300°C postdeposition anneal, the capacitors had the following properties: ε_r=17-18 and tanδ<0.01 up to 600 MHz, J_leak=0.06-0.5 μA/cm² at 0.5 MV/cm, and breakdown field E_max=3.3 MV/cm     

Effects of post-deposition annealing on the electrical propertiesand reliability of ultrathin chemical vapor deposited Ta2O5 films

This paper reports the effects of post-deposition rapid thermal annealing on the electrical characteristics of chemical vapor deposited (CVD) Ta₂O₅ (~10 nm) on NH₃-nitrided polycrystalline silicon (poly-Si) storage electrodes for stacked DRAM applications. Three different post-deposition annealing conditions are compared: a) 800°C rapid thermal O₂ annealing (RTO) for 20 sec followed by rapid thermal N₂ annealing (RTA) for 40 sec, b) 800°C RTO for 60 sec and c) 900°C RTO for 60 see. Results show that an increase in RTO temperature and time decreases leakage current at the cost of capacitance. However, over-reoxidation induces thicker oxynitride formation at the Ta₂O₅/poly-Si interface, resulting in the worst time-dependent dielectric breakdown (TDDB) characteristics     

Structural and Electrical Characters of Ba0.6Sr0.4TiO3/La0.5Sr0.5CoO3 Thin Films by Plus Laser Deposition

Epitaxial Ba0.6Sr0.4TiO3 (BST) thin films were deposited on LaAlO3 (LAO) substrates with the conductive metallic oxide La0.5Sr0.5CoO3 (LSCO) film as a bottom electrode by pulsed laser deposition (PLD). X-ray diffraction ~2 and Ф scan showed that the epitaxial relationship of BST/LSCO/LAO was [001] BST//[001] LSCO//[001] LAO. The atomic force microscope (AFM) revealed a smooth and crack-free surface of BST films on LSCO-coated LAO substrate with the average grain size of 120 nm and the RMS of 1.564 nm for BST films. Pt/BST/LSCO capacitor was fabricated to perform CapacitanceVoltage measurement indicating good insulating characteristics. For epitaxial BST film, the dielectric constant and dielectric loss were determined as 471 and 0.03, respectively. The tunabilty was 79.59% and the leakage current was 2.6310-7 A/cm2 under an applied filed of 200 kV/cm. Furthermore, it was found that epitaxial BST (60/40) films demonstrate well-behaved ferroelectric properties with the remnate polarization of 6.085 C/cm2 and the coercive field of 72 kV/cm. The different electric properties from bulk BST (60/40) materials with intrinsic paraelectric characteristic are attributed to the interface effects.     

Structural and Electrical Characters of Ba0.6Sro.4TiO3/La0.5Sr0.5CoO3 Thin Films by Plus Laser Deposition

Epitaxial Ba0.6Sr0.4TiO3 (BST) thin films were deposited on LaAlO3 (LAO) substrates with the conductive metallic oxide La0.5Sr0.5CoO3 (LSCO) film as a bottom electrode by pulsed laser deposition (PLD). Xray relationship of BST/LSCO/LAO was [001] BST//[001]LSCO//[001] LAO. The atomic force microscope (AFM)revealed a smooth and crackfree surface of BST films on LSCOcoated LAO substrate with the average grain size of 120 nm and the RMS of 1.564 nm for BST films.Pt/BST/LSCO capacitor was fabricated to perform CapacitanceVoltage measurement indicating good insulating characteristics. For epitaxial BST film, the dielectric constant and dielectric loss were determined as 471 and 0.03, respectively. The tunabilty was 79.59% and the leakage current was 2.63×107 A/crm2 under an applied filed of 200 kV/cm. Furthermore, it was found that epitaxial BST (60/40) films demonstrate wellbehaved ferroelectric properties with the remnate polarization of 6.085 μC/cm2 and the coercive field of 72 kV/cm. The different electric properties from bulk BST (60/40)materials with intrinsic paraelectric characteristic are attributed to the interface effects.     

Effects of post-deposition anneal on the electrical properties ofSi3N4 gate dielectric

The effects of postdeposition anneal of chemical vapor deposited silicon nitride are studied. The Si₃N₄ films were in situ annealed in either H₂(2%)/O₂ at 950°C or N₂O at 950°C in a rapid thermal oxidation system. It is found that an interfacial oxide was grown at the Si₃N₄/Si interface by both postdeposition anneal conditions. This was confirmed by thickness measurement and X-ray photoelectronic spectroscopy (XPS) analysis. The devices with H₂ (2%)/O₂ anneal exhibit a lower gate leakage current and improved reliability compared to that of N₂O anneal. This improvement is attributed to a greater efficiency of generating atomic oxygen in the presence of a small amount of hydrogen, leading to the elimination of structural defects in the as-deposited Si₃N ₄ film by the atomic oxygen. Good drivability is also demonstrated on a 0.12 μm n-MOSFET device     

RuO2/GaN Schottky contact formation with superiorforward and reverse characteristics

This is a first time report of a ruthenium oxide (RuO₂) Schottky contact on GaN. RuO₂ and Pt Schottky diodes were fabricated and their characteristics compared. When the RuO₂ Schottky contact was annealed at 500°C for 30 min, the current-voltage (I-V) and capacitance-voltage (C-V) characteristics of the RuO₂ were dramatically improved. The annealed RuO₂ /GaN Schottky contact exhibited a reverse leakage current that was at least two or three orders lower in magnitude than that of the Pt/GaN contact along with a very large barrier height of 1.46 eV, which is the highest value ever reported for a GaN Schottky system     

Impact of time dependent dielectric breakdown and stress-inducedleakage current on the reliability of high dielectric constant(Ba,Sr)TiO3 thin-film capacitors for Gbit-scale DRAMs

Time dependent dielectric breakdown (TDDB) and stress-induced leakage current (SILC) are investigated for the reliability of (Ba,Sr)TiO₃ (BST) thin films. Both time to breakdown (T_BD) versus electric field (E) and T_BD versus 1/E plots show universal straight lines, independent of the film thickness, and predict lifetimes longer than 10 y at +1 V for 50 nm BST films with an SiO₂ equivalent thickness of 0.70 nm. SILC is observed at +1 V after electrical stress of BST films; nevertheless, 10 y reliable operation for Gbit-scale DRAMs is predicted in spite of charge loss by SILC. Lower (Ba+Sr)/Ti ratio is found to be strongly beneficial for low leakage, low SILC, long TBD, and therefore greater long-term reliability. This suggests a worthwhile tradeoff against the dielectric constant, which peaks at a (Ba+Sr)/Ti ratio of 1.05     

Dual Process Dielectric Formation for Decoupling Capacitors on Flexible Substrates

Large area, high density integrated capacitors within printed wiring boards can provide a substantial decoupling capacitance with very low parasitic inductance. Tantalum pentoxide (Ta₂O₅) is an excellent dielectric for this application due to the relatively high dielectric constant (~ 22-24), however the difficulty of fabricating large, defect-free capacitors has thus far prevented the realization of practical applications. This work demonstrates high performance capacitors with Ta₂O₅ dielectric developed with a two step oxidation scheme consisting of reactive sputtering followed by anodization. Thin films of Ta₂O₅ were deposited by reactive sputtering on silicon and also on Upilex^reg covered glass wafers using dc magnetron sputtering with a gas flow ratio of 10/90 O₂/Ar. In the two-step oxidation scheme, anodization is performed after reactively sputtering tantalum oxide films to obtain a densifled oxide structure. The electrical and physical properties of these two step sputtered/ anodized tantalum oxide films are shown to be superior to those of tantalum oxide films prepared by either anodization or sputtering alone. This work has shown that Ta₂O₅ is a potential dielectric for integrated capacitors that could be used in advanced packaging applications.