200V高压大电流VDMOS的研制

介绍了自主研制的200 V/40 A VDMOS晶体管的设计优化过程及研制结果.该器件采用JFET注入和浅P-body方法降低导通电阻,提高电流密度,采用优化的N掺杂硅外延材料优化导通电阻和击穿电压.测试结果表明击穿电压高于215 V,特征导通电阻1.2 Ω·mm2,导通电流可达40 A;同时设计了ESD防护,HBM值...     

基于浮动源的氮化镓器件导通电阻测试技术研究

首先,介绍了氮化镓器件的基本特征,以一款氮化镓功率器件为例,介绍了其基本结构、应用场景和关键参数,并研究了其导通电阻的测试;其次,介绍了浮动源的特点,研究了使用浮动源测试氮化镓器件导通电阻的方法,在测试方案的软件、硬件设计上提出了一些建议;然后,将所提出的测试方案运用于实际测试,结果表明,得到的测试数据与理论值吻合地较好,证明了测试方案的有效性;最后,对测试过程中常见的问题进行了分析,对于提高氮化镓器件导通电阻测试精度具有一定的参考价值。     

磷砷注入对沟槽MOSFET静态参数的影响北大核心

为了降低沟槽MOSFET器件导通电阻，提出了在传统沟槽MOSFET器件体区注入N型杂质的方案，优化了体区杂质浓度分布，从而降低导通电阻。经仿真验证，选择N+源区注入后注入砷，在能量为300 keV,剂量为7×1012cm-2条件下，特征导通电阻能降低13%,阈值电压降低21.8%;选择接触孔刻蚀后注入磷，在能量为100 keV,剂量为4×1012cm-2条件下，特征导通电阻降低4.3%,阈值电压几乎不变。     

晶圆级导通电阻测试精度的改进方法

针对晶圆级导通电阻测试误差过高,满足不了低压金属氧化物半导体场效应晶体管(MOSFET)毫欧级导通电阻的测试精度要求,给产品晶圆测试规范的制定及品质监控带来困扰的问题,提出了晶圆级导通电阻测试精度的改进方法。基于开尔文法电阻测试理论,具体分析了晶圆级导通电阻测试原理,且得出其测试精度不高的根本原因是减薄背金后粗糙不平的硅片背面与测试机的承片台的非充分接触而引入了毫欧级接触电阻。提出3种相应改进测试精度的方法,单相邻芯片辅助的测试方法、双相邻芯片辅助的测试方法和正面漏极测试窗的测试方法。经过验证,3种方法均能将毫欧级导通电阻测试误差控制到小于10%,实现低压MOSFET晶圆级导通电阻参数的有效监测。     

瑞萨推出导通电阻仅为150mΩ的600V耐压超结MOSFET

正瑞萨电子宣布开发出了导通电阻仅为150 mΩ(栅源间电压为10 V时的标称值)的600 V耐压超结(SJ:SuperJunction)型功率MOSFET"RJL60S5系列",将从2012年9月开始样品供货。超结是可在不牺牲耐压的情况下,降低导通电阻的功率MOSFET的元件构造。虽然其他竞争公司已经推出了采用这种构造的功率MOSFET,但据瑞萨电子介绍,"RJL60S5系列"在600 V耐压产品中实现了业界最小水平的导通电阻。马达驱动电路和逆变器等采用RJL60S5系列功率     

测试和测量

直流电气测试系统 2790—A型源表安全气囊充气机直流电气测试系统提供了进行绝缘电阻和导通电阻(电桥标准导线)连续性测试所需要的全部电源、测量、以及信号通道性能,可以测量的范围涵盖1MW～10GW。快速限流性能对测量电路能量进行限制,以避免电压和电流源损坏被测试的产品。     

漏压对P-GaN HEMT导通电阻和阈值电压的影响

为了研究漏极偏压变化对P-GaN器件可靠性的影响,文中对P-GaN商用器件进行漏极应力测试.通过改变漏极应力偏置电压和偏置时间,观察GaN器件导通电阻和阈值电压的变化.测试结果表明,无P-GaN漏极结构的器件导通电阻随着漏极电压变化先增大后减小,而阈值电压几乎不受影响;有P-GaN漏极结构的器件导通电阻几乎不受影响,而...     

一种偏置电路噪声消除的VCO

基于0.18 μm CMOS工艺,设计并制作了一种偏置电路噪声消除的VCO。通过在偏置电路与VCO的尾电流源之间插入选通电路,可以实现对偏置电路的噪声电压的低通滤波。分析表明,该低通滤波器的拐点频率与选通电路的导通电阻、关断电阻以及开关时钟占空比相关。电路测试表明,加入选通电路之后,VCO的近端相噪下降约20 dB,大大降低了偏置电路的相噪贡献。     

采用双层介质膜和两次源漏区注入的高压CMOS模拟开关

本文介绍一种采用全离子注入的CMOS/双极兼容工艺制做的高压低阻值CMOS模拟开关.采用双层介质膜作为栅绝缘膜,可以大大降低导通电阻.在源漏区采用两次注入的办法,可以把栅—漏或栅—源之间的击穿电压从一般的25伏提高到80伏.这种模拟开关可工作在60伏以上,其导通电阻低于15Ω,非线性失真低于-70dB,通阻比大于80dB.     

线性变掺杂高阻漂移区LDMOS导通电阻的建模

首先建立了线性变掺杂高阻漂移区LDMOS的导通电阻的模型,通过分析、计算,得出它的导通电阻的解析表达式,然后用MATLAB软件和MEDICI软件对总导通电阻和各部分电阻进行模拟.经过讨论,得出其性能优于均匀掺杂高阻漂移区LDMOS的结论.     

一种微处理器控制电子引信电路的设计

针对机械式引信系统可靠性低、精度差,以及模拟电子引信系统抗干扰性差等问题,研究设计了一种微处理器控制的电子引信系统.文章以一种多功能引信电路为例,介绍了微处理器控制引信系统的设计及工艺制造.样品的试验结果和使用情况表明,该设计方案切实可行,安全可靠;参数修改、调整灵活便捷;设计思路新颖,并具有推广性.     

多控制器并行处理的安全和起爆电路测试装置

针对现有测试技术一次上电只能完成对单发引信测试且测试过程繁琐的缺点,提出基于多控制器并行处理的安全和起爆电路测试装置.该测试装置通过一台计算机、两个单片机和温度控制器构成了多机通讯控制系统,两个单片机通过相应的电源模块、触发模块和采集模块与多发被测安全和起爆电路相连,多机间通过串口通讯方式进行信息交换,获得多发被测安全和起爆电路的各种测试数据.分析和试验表明该测试装置能够很好的完成对多发被测安全和起爆电路的测试任务,具有测试效率高、实时性强、操作方便快捷、人为误差小等特点.     

Electro thermal modeling of the power diode using Pspice

In this paper, an improved electro thermal model of power diode was developed. The main local physical effects were taken into consideration. The suggested model is able to address the electrical and thermal effects. The model was confirmed through a comparison with other models having close characteristics for different circuits (AC-DC converter, turn-on and turn-off) and different temperatures. The diode was implemented in the Pspice circuit simulation platform using Pspice standard components and analog behavior modeling (ABM) blocks. The diode switching performance was investigated under influence of different circuit elements (such as stray inductance, gate resistance and temperature) in order to study and estimate the on-state and switching losses pre-requisite for the design of various converter and inverter topologies. The comparison shows that these models are simple, tunable with the electric circuit software simulator. They are more capable of predicting the main circuit parameters needed for power electronic design. The transient thermal responses were demonstrated for the single pulse and repeat modes. The achieved results show that our model is suitable for full electro thermal simulations of power electronic circuits.     

基于SMIC40LL工艺的DDR物理层IP设计

随着高性能消费电子如智能手机,平板电脑的迅速普及,对高性能低功耗的DDR接口电路的需求随之迅速增加。本文论述了在SMIC40LL工艺上实现了高性能、低功耗、小面积的DDR物理层IP技术,包括DDR物理层架构、DLL设计、10设计和物理实现。该物理层IP可以在ss条件下达到1333Mbps的速率并在核心电压稍稍过压下达到1600Mbps的速率。     

Evaluation of Packaging-Induced Performance Change for Small-Scale Analog IC

The impact of packaging-induced circuit performance changes for a small-scale integrated circuit (IC) smaller than 1.0 mm $^{2}$ has been evaluated by a new method with specially designed test chips. Analog circuits such as power management ICs for portable electronic devices are small-scale chips and require high-accuracy operation. Multiple test chips with different resistor locations have been fabricated and measured by die-to-die correspondence, after which one distribution chart was reproduced from all of the measurement results. The present method enables the characteristic distribution on the chip surface to visualize not only the electrical parametric distribution but also the residual stress distribution, even though small-scale ICs have a limited number of bonding pads. In addition, a new method for evaluating the circuit performance change of an analog circuit due to stress-induced parametric changes is presented.      

Fully Electrical Modeling of Thermoelectric Generators with Contact Thermal Resistance Under Different Operating Conditions

The Seebeck effect is used in thermoelectric generators (TEGs) to supply electronic circuits by converting the waste thermal into electrical energy. This generated electrical power is directly proportional to the temperature difference between the TEG module’s hot and cold sides. Depending on the applications, TEGs can be used either under constant temperature gradient between heat reservoirs or constant heat flow conditions. Moreover, the generated electrical power of a TEG depends not only on these operating conditions, but also on the contact thermal resistance. The influence of the contact thermal resistance on the generated electrical power have already been extensively reported in the literature. However, as reported in Park et al. (Energy Convers Manag 86:233, 2014) and Montecucco and Knox (IEEE Trans Power Electron 30:828, 2015), while designing TEG-powered circuit and systems, a TEG module is mostly modeled with a Thévenin equivalent circuit whose resistance is constant and voltage proportional to the temperature gradient applied to the TEG’s terminals. This widely used simplified electrical TEG model is inaccurate and not suitable under constant heat flow conditions or when the contact thermal resistance is considered. Moreover, it does not provide realistic behaviour corresponding to the physical phenomena taking place in a TEG. Therefore, from the circuit designer’s point of view, faithful and fully electrical TEG models under different operating conditions are needed. Such models are mainly necessary to design and evaluate the power conditioning electronic stages and the maximum power point tracking algorithms of a TEG power supply. In this study, these fully electrical models with the contact thermal resistance taken into account are presented and the analytical expressions of the Thévenin equivalent circuit parameters are provided.     

IR1150在有源功率因数校正电路中的应用

在开关电源中,加入有源功率因数校正电路,可使功率因数达到0.99以上,并把电源输入电流的波形失真减小到5%以下,大大减小开关电源对电网的污染。IR1150是有源功率因数校正电路专用控制器,其采用单周期控制原理,控制电路简单,易于设计、调试,可大大减小体积、降低成本。文中详细介绍了IR1150的内部电路,管脚排列及功能,还详细分析、设计出400 W的样机。     

矿用电子皮带秤井下计量仪表的设计

为了方便矿用电子皮带秤现场维护,开发了将电气设计和防爆技术相结合的本质安全型计量仪表.介绍了计量仪表以SN75LBC184构建的RS485通讯电路和以CS5532为基础设计的重量信号采集电路,以及基于ASCII编码方式的低误码率数据帧设计方法、RS485通讯程序的设计思路以及CS5532的参数配置和初始化,简要介绍了计...     

Electrical design inspection: a methodology for using circuitsimulation in the design and development of electronic power supplies

The authors present an electrical design inspection (EDI) methodology that combines advanced power circuit simulation techniques and RISC (reduced instruction set computing) workstation hardware to use simulation in the day-to-day design of electronic power supplies. This methodology makes use of circuit simulation to detect design faults in electronic power supplies and prevent them from propagating further in the product realization process. A hierarchy of inspections which form the basis of EDI methodology, is introduced. The methodology has been embedded in a prototype electrical design inspection system which has been tested on a Sun Sparcserver 4/490 dedicated to circuit simulation. The power of this methodology has been illustrated by its application to a self-oscillating variable-frequency DC-DC power converter with peak current control. It is demonstrated that EDIS can automatically execute inspections requiring an accurate determination of the steady-state solution of the circuit, and process these results. The steady-state accelerator capability within the SIMPLIS circuit simulator has made it possible to achieve this in an unprecedentedly short CPU time     

基于符号率动态变频的低功耗DOCSIS上行发射器设计

 为解决DOCSIS上行发射器的高功耗问题,本文在深入剖析信道突发特点和发射器结构的基础上,提出了一种全新的发射器VLSI（超大规模集成电路）设计低功耗体系. 通过引入发射符号率这一性能约束,该体系可使上行数据通路上所有运算电路能根据不同的突发符号率动态调节运算频率,以最小的功耗消耗匹配突发处理的性能要求. 实验结果表明,在不同突发符号率下,所提出体系可使上行发射器的总功耗平均降低67.13%. 本文设计的低功耗上行发射器已应用于符合EuroDOCSIS1.1规范的支持双向有线数字电视点播的Cabl e Modem（CM） SOC（片上系统）平台中,并表现出优良的低功耗特性. 不失一般性,本文所提出的设计体系不仅适用于其他对功耗敏感的通信系统,同时,也将有助于推动超大规模集成电路及SOC设计领域中低功耗这一关键技术的发展.