CMOS APS用移位寄存器抗SEU加固方法

电离辐射环境中使用的CMOS 有源像素图像传感器(APS)的基于反相器的准静态移位寄存器容易发生单粒子翻转(SEU),而致使CMOS APS不能正常工作。本文对基于反相器的准静态移位寄存器中的单粒子翻转效应进行了分析,其对单粒子瞬态(SET)最敏感的节点存在于反相器的输入端,反相器的输入阈值电压和输入节点电容决定了其抗SEU的能力。提出了用施密特触发器代替反相器的加固方案,因施密特触发器的电压传输特性存在一滞回区间,所以有更高的翻转阈值,从而可获得更好的抗SEU能力。仿真结果表明,采用施密特触发器的移位寄存器结构较原电路结构的抗SEU能力提高了约10倍。     

Radiation-Tolerant 50MHz Bulk CMOS VLSI Circuits Utilizing Radiation-Hard Structure Nmos Transistors

A radiation-tolerant, high-speed, bulk CMOS VLSI circuit design, utilizing a new NMOS structure, has been investigated, based on ?-ray irradiation experimental results for 2?m shift registers. By utilizing 60-bit clocked gate and transfer gate static shift register circuits, the usefulness of radiation-hard NMOS structure and circuit design parameter optimization has been confirmed experimentally, showing 50 MHz operation CMOS circuits at 5 V supply voltage after 1 × 105 rads (Si) irradiation. The limitations of dynamic circuits in radiation-tolerant circuit designs have also been shown, using 120-bit dynamic shift register circuits. Based on the above results, radiation-tolerant, high-performance, bulk CMOS VLSI circuit designs are discussed.     

Design Optimization of Radiation-Hardened CMOS Integrated Circuits

Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre-and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented.     

Process Optimization of Radiation-Hardened CMOS Integrated Circuits

The effects of processing steps on the radiation hardness of MOS devices have been systematically investigated. Quantitative relationships between the radiation-induced voltage shifts and processing parameters have been determined, where possible. Using the results of process optimization, a controlled baseline fabrication process for aluminum-gate CMOS has been defined. CMOS inverters which can survive radiation exposures well in excess of 108 rads (Si) have been fabricated. Restrictions that the observed physical dependences place upon possible models for the traps responsible for radiation-induced charging in SiO2 are discussed.     

Radiation Hardened CMOS/SOS Memory Circuits

Large-scale-integrated circuits which combine radiation hardness with density, high speed and low power dissipation require both hardened processes and hardened circuit design methods. CMOS/SOS circuits featuring self-compensation, self-biasing and parameter tracking accommodate a wide range of nonuniform on-chip parameter variations. These variations result from exposure to a nuclear radiation event, as well as from MOS device processing, temperature and power-supply effects. The circuits discussed in this paper are key elements for radiation-hardened memory designs [up to 106 rads(Si)] with state-of-the-art LSI density and performance. The CMOS/SOS memory cell sizes of 3.1 mil2 for a six-device, and 2.5 mil2 for a four-device, static cell are nearly five times smaller than previous radiation-hardened designs.     

Radiation Models for Digital Integrated Circuits

The effort to be described had as its objective the development of new techniques to define simplified models of digital integrated circuits suitable for use with the SCEPTRE or similar computer programs. These models were required to account for normal electrical performance as well as performance in an environment of ionizing and/or neutron radiation. Techniques were established to derive models capable of representing both the radiation effects and the first order transient response of the microcircuits as system components for many different kinds of digital integrated circuits. A "black-box" approach was employed to achieve the desired results.     

Fail-Safe Circuits for Nuclear Protective Systems

The article describes a new set of fail-safe logic blocks particularly suited to safety systems. The input information is normally +5V; in case of alarm, the input drops to 0V. Fundamental blocks (AND, OR, NOT, etc.) are pulse-modulated, so as to achieve 0V output voltage in case of failure. More complex logic function can be synthesized and redundancy can be employed in order to avoid erroneous action.     

Modeling and Test Verification for Hardened Integrated Circuits

Hardened dielectrically isolated integrated circuits are being developed to provide an order of magnitude improvement in radiation response over previous bipolar technology. This paper describes (a) the analytical and experimental techniques used to develop the hardened parts, and (b) comparative analytical and test results obtained thus far in the program. The paper describes how (a) various "element" models were defined for CAD usage, (b) how design tolerances were established for the element models, (c) how circuit design margins were established, (d) experimental techniques and equipment used to validate early designs, and (e) comparative analytical and test results.     

Nanosecond Trigger Circuits

This paper presents a summary of switching properties of high-speed trigger circuits. The introduction of general characteristics is followed by a review of switching in tunnel-diode trigger circuits, and by an analysis of a simple transistor trigger circuit.     

CMOS APS数字模组辐射环境中的屏蔽加固

对互补金属氧化物半导体（CMOS）有源像素传感器（APS）数字模组的辐射耐受性进行了研究,设计并制造了屏蔽加固结构。利用蒙特卡罗模拟软件对屏蔽结构的材料、挡板尺寸以及前挡板开孔孔径进行了设计和计算,并对所设计屏蔽结构的屏蔽性能,加固前后传感器模组的工作寿命以及辐射损伤模式进行了实验研究。实验结果表明:所设计屏蔽结构能够使APS的工作寿命提高约1倍;屏蔽后,主板的受照剂量率约为无屏蔽时的1/3,但其工作寿命仅提高约1倍,这可能是由于模组上各器件的耐辐射性能以及受照剂量存在差异导致的;当辐照总剂量小于50?Gy时暗电流几乎无变化,当总剂量大于150?Gy后APS各像素的暗电流逐渐增大。      

具有高计数率性能的ECT闪烁探测器前端电路

介绍了几种可以提高ECT闪烁探测系统计数率性能的前放电路设计,包括延迟线渐波法（DLC）、动态积分法（DIM）和脉冲堆积防止法（PPM）,并给出了它们的性能比较。     

井下中子发生器电路研究

本文对Ｃ／Ｏ比（碳／氧比）井下中子发生器离子源电路的靶极高压电路进行了深入研究，结果表明：离子源电路采用反激式变换电路更合理，提出了确定靶极高压倍加电路最佳工作点的方法。     

CMOS工艺X射线图像传感器设计

本文设计了一种不需闪烁体或增感屏,直接对X射线进行探测成像的线阵图像传感器,对其电荷收集进行了理论分析,设计了辐射加固的光敏元结构。采用0.5 μm DPTM CMOS工艺,针对单个像元内含不同个数光敏元的结构进行了流片和X射线实验测试。测试结果表明：该图像传感器暗信号电压约为1 V,随像元内光敏元个数的增加暗信号电压增大;饱和输出电压为2.4 V;随光敏元个数的增加,电荷收集总量增加,总寄生电容也同时增加,所设计的单个像元含3个光敏元的结构能得到相对更大的有效输出电压。     

CMOS硅像素探测器测试系统设计

针对环形正负电子对撞机(CEPC)最内层的顶点探测器而研制的CMOS硅像素探测器已经提交首次流片。为了采集探测器的数据进而研究前端芯片的性能,基于现场可编程逻辑门阵列(FPGA)设计高速数据传输的测试系统,该系统以PCI Express总线模式进行高速传输数据。对系统性能的测试表明:数据传输速度能达到6Gb/s,传输的数据量和误码率性能均满足CMOS硅像素探测器芯片的测试要求。     

两类多丝室读出电路的研究

从不同应用目的出发,本文介绍了二类多丝室的读出电路和系统。     

BES漂移室读出电子学逻辑控制及扇出电路

本文阐述了北京谱仪(BES)漂移室读出电子学逻辑控制和扇出电路的原理及技术性能,介绍了逻辑控制电路的系统校准和数据获取的两种工作方式。实验表明,它可有效地完成6834电子学通道的逻辑控制。