Low-Temperature Silicon-to-Silicon Anodic Bonding Using Sodium-Rich Glass for MEMS Applications

In the present work, silicon-to-silicon anodic bonding has been accomplished using an intermediate sodium-rich glass layer deposited by a radiofrequency magnetron sputtering process. The bonding was carried out at low direct-current voltage of about 80 V at 365°C. The alkali ion (sodium) concentration in the deposited film, the surface roughness of the film, and the flatness of the silicon wafers were studied in detail and closely monitored to improve the bond strength of the bonded silicon wafers. The effect of chemical mechanical polishing (CMP) on the surface roughness of the deposited film was also investigated. The average roughness of the deposited film was found to be ~6 Å, being reduced to 2 Å after CMP. It was observed that the concentration of sodium ions in the deposited film varied significantly with the sputtering parameters. Scanning electron microscopy was used to obtain cross-sectional images of the bonded pair. The bonding energy of the bonded wafer pair was measured using the crack-opening method. The bonding energy was found to vary from 0.3 J/m² to 2.1 J/m² for different bonding conditions. To demonstrate the application of the process developed, a sealed cavity was created using the silicon-to-silicon anodic bonding technique, which can be used for fabrication of devices such as capacitive pressure sensors and Fabry– Perot-based pressure sensors. Also, a matrix of microwells was fabricated using this technique, which can be used in various biomicroelectromechanical system applications.     

无压力辅助硅/玻璃激光局部键合

提出了一种新的无需外压力作用的硅/玻璃激光局部键合方法,通过对晶圆进行表面活化处理,选择合适的激光参数及加工环境,成功地实现了无压力辅助硅/玻璃激光键合.同时研究了该键合工艺参数如激光功率、激光扫描速度、底板材料等的影响.实验表明,激光功率越大,扫描速度越小,键合线的宽度就越大.实验结果显示,该方法能有效减少键合片的残余应力,控制键合线宽,并能得到较好的键合强度.该工艺可为MEMS器件的封装与制造提供简洁、快速、键合区可选择的新型键合方法.     

无压力辅助硅/玻璃激光局部键合

提出了一种新的无需外压力作用的硅/玻璃激光局部键合方法,通过对晶圆进行表面活化处理,选择合适的激光参数及加工环境,成功地实现了无压力辅助硅/玻璃激光键合.同时研究了该键合工艺参数如激光功率、激光扫描速度、底板材料等的影响.实验表明,激光功率越大,扫描速度越小,键合线的宽度就越大.实验结果显示,该方法能有效减少键合片的残余应力,控制键合线宽,并能得到较好的键合强度.该工艺可为MEMS器件的封装与制造提供简洁、快速、键合区可选择的新型键合方法.     

低温阳极键合工艺研究

对低温阳极键合特性进行了研究.通过对硅片进行亲水、疏水和表面未处理3 种不同处理方式研究其对键合的影响,键合前将硅片浸入去离子水（DIW）中不同时间,研究硅表面H基和氧化硅分子数量对键合的影响.结果表明经亲水处理的硅片在水中浸泡1 h 的键合效果最佳.并设计了不同烘烤时间下的阳极键合实验,表明在100 °C 下烘烤30 min 可以有效减少气泡的数量和尺寸.由不同工艺条件下得到的键合形貌可知,通过控制硅片表面微观状态可以达到减小或消除键合气泡的目的.     

Low temperature glass-to-glass wafer bonding

In this paper, results of successful anodic bonding between glass wafers at low temperature are reported. Prior to bonding, a special technique was used, i.e., an amorphous and hydrogen free silicon film was deposited on one of the glass wafers using a sputtering technique. The effects of bonding temperature and voltage were investigated. The bonding temperature and the voltage applied ranged from 200/spl deg/C to 300/spl deg/C and 200 V to 1000 V, respectively. As the bonding temperature and bonding voltage increased, both the unbonded area and the size of voids decreased. Scanning electron microscope (SEM) observations show that the two glass wafers are tightly bonded. The bond strength is higher than 10 MPa for all the bonding conditions. Furthermore, the bond strength increases with increasing bonding temperature and voltage. The study indicates that high temperature and voltage cause more Na/sup +/ ions to neutralize at the negative electrode, which leads to higher charge density inside the glass wafer. Furthermore, the transition period to the equilibrium state also becomes shorter. It is concluded that the anodic bonding mechanisms involve both oxidation of silicon film and the hydrogen bonding between hydroxyl groups.     

Selective bonding and encapsulation for wafer-level vacuum packaging of MEMS and related micro systems

A laser-assisted bonding technique is demonstrated for low temperature region selective processing. A continuous wave carbon dioxide (CO₂) laser (λ=10.6 μm) is used for solder (Pb37/Sn63) bonding of metallized silicon substrates (chips or wafers) for MEMS applications. Laser-assisted selective heating of silicon led to the reflow of an electroplated, or screen-printed, intermediate solder layer which produced silicon–solder–silicon joints. The bonding process was performed on fixtures in a vacuum chamber at an air pressure of 10⁻³ Torr to achieve fluxless soldering and vacuum encapsulation. The bonding temperature at the sealing ring was controlled to be close to the reflow temperature of the solder. Pull test results showed that the joint was sufficiently strong. Helium leak testing showed that the leak rate of the package met the requirements of MIL-STD-883E under optimized bonding conditions and bonded packages survived thermal shock testing. The testing, based on a design of experiments method, indicated that both laser incident power and scribe velocity significantly influenced bonding results. This novel method is especially suitable for encapsulation and vacuum packaging of chips or wafers containing MEMS and other micro devices with low temperature budgets, where managing stress distribution is important. Further, released and encapsulated devices on the sealed wafers can be diced without damaging the MEMS devices at wafer level.     

Infrared spectroscopy of bonded silicon wafers

Infrared spectra of multiple frustrated total internal reflection and transmission for silicon wafers obtained by direct bonding in a wide temperature range (200–1100°C) are studied. Properties of the silicon oxide layer buried at the interface are investigated in relation to the annealing temperature. It is shown that the thickness of the SiO₂ layer increases from 4.5 to 6.0 nm as the annealing temperature is increased. An analysis of the optical-phonon frequencies showed that stresses in the SiO₂ relax as the annealing temperature is increased. A variation in the character of chemical bonds at the interface between silicon wafers bonded at a relatively low temperature (20–400°C) is studied in relation to the chemical treatment of the wafers’ surface prior to bonding. Models of the process of low-temperature bonding after various treatments for chemical activation of the surface are suggested.     

Effective cleaning process and its influence on surface roughness in anodic bonding for semiconductor device packaging

Wafer cleanliness and surface roughness play a paramount role in an anodic bonding process. Impurities and the roughness on the wafer surface result in unbonded areas which lead to fringes and Newton׳s rings. With an augment in surface roughness, lesser area will be in stroke thus making more pressure and voltage to be applied onto the wafers for better bonding. Eventually it became mandatory to choose the best cleaning process for the bonding technology that can substantially reduce the impurities and surface roughness. In this paper, we investigate the bonding of silicon/oxidized silicon on Pyrex (CORNING 7740) glass with respect to surface roughness and cleanliness of the wafers by performing three renowned cleaning processes such as degreasing, piranha, RCA 1& 2 (SC‐Standard Cleaning 1 and 2) and found that RCA compromises the best between the roughness and cleanliness. Studies were also extended to find out the effects of applied voltage and load on the bonded surface. It was observed for samples cleaned with RCA, an increase of 45% in maximum current and decrease of 75% in total bonding time with the applied load and voltage among all the cleaning techniques used. Three dimensional structures for pressure sensor application were successfully bonded by selecting the appropriate load and cleaning process. Atomic force microscopy analysis was done to investigate the surface roughness on silicon/oxidized silicon and Pyrex glass for different cleaning processes. Scanning electron microscopy and optical imaging were performed on the interface for the surface integrity of the bonded samples.     

Effect of nanotopography in direct wafer bonding: modeling and measurements

Nanotopography, which refers to surface height variations of tens to hundreds of nanometers that extend across millimeter-scale wavelengths, is a wafer geometry feature that may cause failure in direct wafer bonding processes. In this work, the nanotopography that is acceptable in direct bonding is determined using mechanics-based models that compare the elastic strain energy accumulated in the wafer during bonding to the work of adhesion. The modeling results are presented in the form of design maps that show acceptable magnitudes of height variations as a function of spatial wavelength. The influence of nanotopography in the bonding of prime grade silicon wafers is then assessed through a combination of measurements and analysis. Nanotopography measurements on three 150-mm silicon wafers, which were manufactured using different polishing processes, are reported and analyzed. Several different strategies are used to compare the wafers in terms of bondability and to assess the impact of the measured nanotopography in direct bonding. The measurement and analysis techniques reported here provide a general route for assessing the impact of nanotopography in direct bonding and can be employed when evaluating different processes to manufacture wafers for bonded devices or substrates.     

Si/Si键合界面的超声显微成像(英文)

硅/硅键合片在MEMS器件的生产中得到了应用。如果硅片的表面被微观粒子或被污染液体中的残余物所沾污,硅/硅键合界面就会产生空洞。如果这些空洞没有被及时发现,将给后道工序带来严重的问题,并降低成品率。超声显微成像对于不同材料的界面反应非常敏感,对硅/硅界面存在的空洞很容易声学成像。使用超声显微成像能够检测到键合界面存在的空洞,因而可以把有缺陷的硅片在造成进一步的损失之前清除掉。高分辨率的超声显微成像可以辨别出直径5μm的空洞。     

Intermediate wafer level bonding and interface behavior

The paper presents a new silicon wafer bonding technique. The high-resolution bonding pad is defined through photolithography process. Photosensitive materials with patternable characteristics are served as the adhesive intermediate bonding layer between the silicon wafers. Several types of photosensitive materials such as SU-8 (negative photoresist), AZ-4620 (positive photoresist), SP341 (polyimide), JSR (negative photoresist) and BCB (benzocylbutene) are tested and characterized for their bonding strength. An infrared (IR) imaging system is established to examine the bonding results. The results indicate that SU-8 is the best bonding material with a bonding strength up to 213 kg/cm² (20.6 MPa) at bonding temperature less than 90 °C. The resolution of bonding pad of 10 μm can be achieved. The developed low temperature bonding technique is particularly suitable for the integration of microstructures and microelectronics involved in MEMS and VLSI packaging processes.     

Wafer bonding for III–V on insulator structures

The InP and GaAs wafers were bonded to GaAs substrates using a siliconnitride intermediate layer. Key process parameters include the silicon-nitride surface roughness and density as determined by atomic-force microscopy and x-ray reflectivity. We demonstrate that silicon nitride can be bonded without any chemical-mechanical polishing step. Silicon-nitride films produced by plasma-enhanced chemical-vapor deposition (PECVD) and deposition by sputtering were compared for bonding compatibility. Smooth silicon-nitride layers (root-mean-square roughness <0.7 nm) were found to produce large areas of bonded material and an oxygen-plasma treatment (200 mtorr, 200 W, 60 s) produced strong nitride/nitride bonding. The strain in the InP layer after transfer to the GaAs substrate was determined using x-ray reciprocal-space mapping (RSM). The crystalline quality of the InP layer was examined with high-resolution x-ray scattering.     

Phase transformations during the Ag-In plating and bonding of vertical diode elements of multijunction solar cells

The conditions of the bonding of silicon multijunction solar cells with vertical p-n junctions using Ag-In solder are studied. The compositions of electrodeposited indium films on silicon wafers silver plated by screen printing and silver and indium films fabricated by layer-by-layer electrochemical deposition onto the surface of silicon vertical diode cells silver plated in vacuum are studied. Studying the electrochemical-deposition conditions, structure, and surface morphology of the grown layers showed that guaranteed bonding is provided by 8-min heat treatment at 400°C under the pressure of a stack of metallized silicon wafers; however, the ratio of the indium and silver layer thicknesses should not exceed 1: 3. As this condition is satisfied, the solder after wafer bonding has the InAg₃ structure (or InAg₃ with an Ag phase admixture), due to which the junction melting point exceeds 700°C, which guarantees the functioning of such solar cells under concentrated illumination.     

Copper bonded layers analysis and effects of copper surface conditions on bonding quality for three-dimensional integration

In order to achieve copper wafer bonding with good quality, surface conditions of copper films are important factors. In this work, the effects of surface conditions, such as surface roughness and oxide formation on the bond strength, were investigated under different bonding conditions. Prior to bonding, copper film surfaces were kept in the atmosphere for less than 1 min, 3 days, and 7 days, respectively, to form different thicknesses of oxide on the surface. Some copper wafers were cleaned using HCl before bonding in order to remove the surface oxide. Surface roughness of copper films with and without HCl cleaning was examined. Since surface cleaning before bonding removes oxides but creates surface roughness, it is important to study the corresponding bond strength under different bonding conditions. These results offer the required information for the process design of copper wafer bonding in three-dimensional integration applications.     

硅/硅直接键合的界面应力

硅/硅直接键合技术广泛应用于SOI,MEMS和电力电子器件等领域,键合应力对键合的成功和器件的性能产生很大的影响。键合过程引入的应力主要是室温下两硅片面贴合时表面的起伏引起的弹性应力;高温退火阶段由于两个硅片的热膨胀系数不同引起的热应力和由于界面的本征氧化层或与二氧化硅键合时二氧化硅发生粘滞流动引起的粘滞应力。另外,键合界面的气泡、微粒和带图形的硅片键合都会引入附加的应力。     

Surface integrity and removal mechanism of silicon wafers in chemo-mechanical grinding using a newly developed soft abrasive grinding wheel

A new soft abrasive grinding wheel (SAGW) used in chemo-mechanical grinding (CMG) was developed for machining silicon wafers. The wheel consisted of magnesia (MgO) soft abrasives, calcium carbonate (CaCO₃) additives and magnesium oxychloride bond. Surface topography, roughness and subsurface damage of the silicon wafers ground using the new SAGW were comprehensively investigated. The results showed that the grinding with the new SAGW produced a surface roughness of about 0.5 nm in R_a and a subsurface damage layer of about 10 nm in thickness, which is comparable to that produced by chemo-mechanical polishing. This study also revealed that the chemical reactions between MgO abrasive, CaCO₃ additives and silicon material did occur during grinding, thereby generating a soft reactant layer on the ground surface. The reactant layer was easily removed during the grinding process.     

Bonding of silicon with filled and unfilled polymers based on black silicon

A bonding method for silicon wafers with unfilled and filled polymer components using `Black Silicon' is presented. The working principle is an interconnection of `Black Silicon' surfaces with ductile materials. Needles of nanostructured `Black Silicon' with their increased surface and undercut features penetrate the polymer when applying pressure. Plastic deformations of the polymer lead to a permanent bond. The retention force exceeds 1000 N/cm² as experiments with polypropylene and low temperature co-fired ceramic tapes (polymer filled with ceramic) show. The application areas are smart packaging, fluidic interconnects for microsystems, electronic assembly and hybrid polymer-ceramic silicon systems     

Near-surface effects of gold in silicon

Gold was introduced into silicon wafers by diffusion from the back surface. The voltage threshold for inversion, near-surface doping density, carrier-generation lifetime, and surface generation velocity were studied by C–VandC-t techniques. Carrier-density profiles were obtained from spreading resistance measurements. The threshold-voltage shifts found are consistent with the introduction by gold of negative charges at the Si/SiO₂ interface. By preparing samples where strong carrier-compensation effects are measured, one enters a regime of high sensitivity of silicon resistance to gold-concentration changes. We infer a negative gold-concentration gradient as one proceeds from the surface into the bulk. The gold concentration continues to change at least up to 17 h at 900°C, with a time constant characteristic of the substitutional diffusion of gold in silicon. The reciprocal of the generation lifetime and the surface generation velocity increase approximately as the gold concentration. Lifetime decreases are limited substantially (by a factor of about 10 for a shallow doping density of 10¹⁴ cm⁻³) for samples of low doping density if strong compensation effects are to be avoided. In spite of the inferred subtle rearrangements in gold concentration lasting many hours, the generation lifetime is independent of gold diffusion time at 900°C within experimental uncertainty in the interval sampled (10–1000 min).