半导体集成电路标准概述

半导体集成电路是半导体器件两大产业之一，对电子电气产业发展有着重要影响。主要介绍了半导体集成电路的产业现状。国内外相关标准概况以及标准发展动向等。     

集成电路的电磁兼容测量标准及需求分析

探讨了集成电路电磁兼容测量标准研究的意义与需求分析,及其对产业发展的影响;介绍了集成电路电磁兼容测量的标准体系.以及标准的发展.     

集成电路的电磁兼容测试标准及需求分析

探讨了集成电路电磁兼容测量标准研究的意义与需求分析,及其对产业发展的影响;介绍了集成电路电磁兼容测量的标准体系,以及标准的发展。     

集成电路电磁兼容测试PCB设计

PCB设计为集成电路电磁兼容测试过程中的一个重要环节,对测试结果的精确度有很大影响,并且与常规PCB设计又有比较大的差异.为提高集成电路电磁兼容测试数据的精准度,基于ICEMC测试标准中对PCB设计的要求,对测试PCB设计中的问题进行了研究分析及解决方法验证,给出了三种屏蔽方法设计方案,明确了过孔间距约束的计算方法,提出去耦电容选型原则及I/0负载匹配方法.通过典型测试案例,从PCB结构设计、布局及布线三个方面进行了详细阐述.旨在为IC研发人员和电磁兼容检测人员提供指导和参考.     

集成电路电磁兼容标准工作组2022年第四次会议

全国半导体器件标准化技术委员会集成电路分技术委员会(SAC/TC78/SC2)下属的集成电路电磁兼容标准工作组(以下简称“工作组”)2022年第四次会议于6月23~24日在线上召开,工作组组员及组员代表共86人出席了会议,会议由工作组归口单位中国电子技术标准化研究院的崔强主持。     

集成电路电磁兼容标准工作组召开2022 年年会

11月17日,全国半导体器件标准化技术委员会集成电路分技术委员会(SAC/TC78/SC2)下属的集成电路电磁兼容标准工作组(以下简称“工作组”)在线上召开2022年年会,工作组组员及组员代表共97人出席了会议,会议由工作组归口单位中国电子技术标准化研究院的崔强主持。工作组秘书处做了工作组2022年工作总结及2023年工作计划。2022年报批了7项国家标准,在研11项国家标准,申报2项国家标准。2023年计划申报GB/T XXXXX-XXXX《集成电路电磁兼容建模第4部分:集成电路射频抗扰度特性仿真模型传导抗扰度建模》等3项国家标准。     

集成电路技术发展对电磁兼容的影响

介绍了集成电路制造业发展的主要趋势,包括复杂度、工作频率、器件性能、供电电压以及器件之间数据交换等。总结了微米级到纳米级CMOS工艺集成电路性能对应的工艺发展节点,讨论了技术演变对集成电路电磁兼容(EMC)的影响,并基于最近几年发表的一系列学术论文综述了集成电路电磁兼容的研究现状。     

集成电路中的电磁兼容（EMC）设计

介绍了集成电路的EMC 问题和EMC 设计方法,重点论述了在集成电路研制过程中,在电路、版图、封装设计 各个阶段EMC 设计的要点。     

An overview of standards in electromagnetic compatibility for integrated circuits

The characterization of the electromagnetic compatibility (EMC) performance of integrated circuits (ICs) is receiving increasing focus as new applications and technology trends combine to raise the complexity of EMC compliance. The increased focus is driving the need for standardized measurement procedures to enable consistent evaluation and comparison of different devices. This paper discusses the need for standardization, describes the work in process by IEC TC47/SC47A Working Group 9 to standardize emissions and immunity EMC test methods for ICs, and examines trends in IC EMC.     

Comparison among emission and susceptibility reduction techniques for electromagnetic interference in digital integrated circuits

This paper presents a comparative study of susceptibility reduction techniques for electromagnetic interference (EMI) in digital integrated circuits (ICs). Both direct power injection (DPI) and very-fast transmission-line pulsing (VF-TLP) methods are used to inject interference into the substrate of a single test chip. This IC is built around six functionally identical cores, differing only by their EMI protection strategies (RC protection, isolated substrate, meshed power supply network) which were initially designed for low emission design rules. The ranking of three of these cores in terms of electromagnetic immunity is then compared with the one of their radiated emission, thanks to near-field scanning (NFS) measurements. This leads to the establishing of design guidelines for low EMI in digital ICs.     

Issues in electromagnetic compatibility of integrated circuits: emission and susceptibility

This paper is focused on the electromagnetic compatibility (EMC) of integrated circuits. The introduction gives general keyword definitions and principles for emission and susceptibility. The second part deals with the evolution of integrated circuit design and technology with its consequences on EMC. The third part describes the mechanisms for generating parasitic noise within integrated circuits and the role of the package and on-chip supply network. Next, the standardized measurement methods are described for both parasitic emission characterization (conducted and radiated) and immunity from 1 MHz to 1 GHz. Issues and proposals up to 18 GHz are discussed. The advances in modeling of emission are also addressed, as well as the issues in immunity prediction.     

A comprehensive simulation model for immunity prediction in integrated circuits with respect to substrate injection

This paper presents a comprehensive modelling methodology for the electromagnetic immunity of integrated circuits (ICs) to direct power injection (DPI). The aim of this study is to predict the susceptibility of ICs by the means of simulations performed on an appropriate electrical model of different integrated logic cores located in the same die. These cores are identical from a functional point of view, but differ by their design strategies. The simulation model includes the whole measurement setup as well as the integrated circuit under test, its environment (PCB, power supply) and the substrate model of each logic core. Simulation results and comparisons with measurement results demonstrate the validity of the suggested model. Moreover, they highlight the interest of the aforementioned protection strategies against electromagnetic disturbances.     

REGINA test mask: research on EMC guidelines for integrated automotive circuits

This paper presents the results obtained with a specific test mask designed at Motorola for the study of the electromagnetic parasitic emissions in integrated circuits (IC). First, origins of parasitic emissions are presented for CMOS circuits, and electromagnetic compatibility (EMC) measurements of IC emissions are detailed: a radiated measurement method with respect to the IEC61967-2 standard and a conducted one with respect to the IEC61967-4 standard. The REGINA test chip is then described, with a focus on particular structures allowing to test and verify some design guidelines for EMC, like delay cell, emissive structure or on-chip sensor. The printed circuit board that is use to implement the test chip and the experiment test bench are also described. A set of measurements is presented and some guidelines are deduced and recommended as design rules.     

Influence of the power supply on the radiated electromagnetic emission of integrated circuits

Ground bounce as a result of fast switching currents is on of the main source for the electromagnetic emission of an integrated circuit. One common method to reduce the ground bounce amplitude is the use of on-chip decoupling capacitors. Besides of this measure other concepts, like the use of different power supply pins, are supposed to reduce ground bounce too. But for all of these measures detail knowledge for the optimal use does not exists so far. In this paper we present a test chip as well as a measurement method for investigations on these measures towards future design guidelines.     

The application of rapid thermal processing technology to the manufacture of integrated circuits—An overview

Like many of the technologies used to process integrated circuits, the road to manufacturing for rapid thermal processing (RTP) has been twisted. What began as a speculative laboratory apparatus has evolved into a cornerstone of IC technology. Qualities that make RTP desirable for IC manufacture include the ability to process wafers individually, the ability to minimize the time wafers spend at elevated temperature, the convenience of clustering RTP to other systems, and the possibility of maintaining cold reactor walls. This paper will review how these properties make RTP desirable. The paper also will present an overview of the difficulties surrounding the use of RTP and describe how many serious hurdles have been overcome. It will summarize the evolution of RTP from a curiosity to a mainstay technology in building integrated circuits. It then will describe SEMATECH’s role in working with RTP, ending with a direction for future application of RTP based on the National Technology Roadmap for Semiconductors (NTRS).     

电磁兼容屏蔽测量技术

当今各种电子、电气设备已广泛应用于人们的日常生活, 随着电气与电子工程技术迅速发展,电磁噪声和电磁干扰问题逐渐引起人们的高度重视,因此,进行电磁兼容测量和实验成为一项非常重要的工作,世界各国都在不断加强电磁兼容技术方面的研究.早期的电磁兼容辐射发射和敏感度测量在开阔场进行,但是随着环境电磁噪声的不断增强,很难找到符合标准的开阔地,近年来,屏蔽测量技术得到了较快发展.本文讨论了电磁兼容测量中屏蔽测量技术的发展,介绍了屏蔽测量技术的原理、应用、现状以及发展趋势,供有关技术人员参考.随着各国对电磁环境重视程度的增加,电磁兼容测量技术将会得到更快的发展.