Tunable dispersion equalizer with a divided thin-film heater for40-Gb/s RZ transmissions

We have developed tunable dispersion equalizers with a chirped fiber grating on the divided thin-film heater. The divided thin-film heater took an important role in the control of dispersion and dispersion slope. We successfully demonstrated the dispersion control from -304 to -196 ps/nm, the dispersion slope control from +100 to -300 ps/nm², and good performance in 40-Gb/s return-to-zero transmission by using this tunable dispersion equalizer     

A 2.5-ns, 40-mW, 4/spl times/4 GaAs multiplier in two's complement mode

The design, fabrication, and testing of a very fast GaAs 4/spl times/4 parallel multiplier based on the modified Booth's algorithm are described. The multiplier includes novel transfer logic cells and is the first high-performance GaAs two's-complement multiplier. The circuit, fabricated with 1-/spl mu/m aligned process, exhibits a multiplication time of 2.5 ns (typical 2.7 ns) on the critical path, with a 40-mW power consumption. Per gate the average delay is 120 ps, at 0.2-mW dissipation.     

A CMOS 1/spl times/-16/spl times/ speed DVD write channel IC

Optical recording demands a meticulous write strategy to control the laser beam power and regulate the phase change layer temperature tightly. The width, height, and delay of a string of short pulses applied to the laser diode need to be adjusted in fine steps, and the writing speed varies widely per applications. A multi-phase phase-locked loop (PLL) tracks a wide range of clock frequencies, and provides a low-jitter time base for write pulses. With two enabling circuit concepts, PLL loop filter voltage folding/unfolding and switch-in of parallel MOS resistors in delay cells, it is possible to operate a PLL to cover a frequency range spanning over three octaves with one VCO. A 10-stage differential VCO is phase-locked to the input channel clock ranging from 26 to 420 MHz (1/spl times/-16/spl times/ DVD speed), and its 20-phase outputs are used to generate write pulses. The pulsewidth and delay are programmed with 120 /spl plusmn/ 40 ps time resolution. The prototype chip fabricated in 0.35 /spl mu/m CMOS occupies 3.5/spl times/3.3 mm/sup 2/, and consumes 294 mW at 3.3 V.     

Postdetection Adjustable Simultaneous Compensation of DGD and GVD in a 40-Gb/s Optical Single-Sideband System

Results on postdetection compensation of group velocity dispersion (GVD) and differential group delay (DGD) in a 40-Gb/s optical single-sideband system are presented. An electrically adjustable transversal filter structure and a microstrip line are used as electrical compensators. Our results show that 408 ps/nm of GVD or 18 ps of DGD, considered separately, are compensated with less than 1.3-dB optical signal-to-noise ratio (OSNR) penalty to back-to-back without compensator, for an extinction ratio (ER) of 6 dB. The simultaneous effect of 12.3 ps of DGD and 374 ps/nm of GVD is compensated with less than 2-dB OSNR penalty, also for ER of 6 dB. Simulations performed support the experimental results.     

1.6 Tbit/s(40×40 Gbit/s)光通信传输系统

在国家自然科学基金网(NSFCNet)上已实现由400 km×10 Gbit/s传输链路直接升级的一路400 km×40 Gbit/s光传输实验的基础上,采用自行研制的40×40 Gbit/s载波抑制归零(CS-RZ)码多波长光发送源,进行了160 km的1.6 Tbit/s(40×40 Gbit/s)波分复用(WDM)光传输实验。实验结果表明,对于常规中短距离10 Gbit/s传输链路可以直接升级至40 Gbit/s。但是由于40 Gbit/s传输系统的色散容限小于60 ps/nm,而且传输光纤与色散补偿模块的色散斜率不匹配,要实现40通道40 Gbit/s的传输,必须对40个信道分别进行精细的色散补偿。这也说明,对于宽带的40 Gbit/s多波长系统,有必要优化设计或更新传输链路。     

40 Gbit/s/ch 2/spl times/2 switch IC using InP HEMTs

A low-power 2/spl times/2 switch IC using InP HEMTs as cold FETs is presented. It has a logic-level-independent interface since no signal line is grounded. The IC yields low insertion loss of 1.5-2.7 dB and high isolation of >21.2 dB below 30 GHz. When two 40 Gbit/s signals were input, error-free operation was confirmed with virtually zero power dissipation.     

Oxide-confined 850 nm VCSELs operating at bit rates up to 40 Gbit/s

Oxide-confined 850 nm vertical-cavity surface-emitting lasers operating at 40 Gbit/s at current densities ~10 kA/cm² are realised. The deconvoluted rise time of the device is below 10 ps and remains hardly temperature sensitive up to 100degC.     

Rational harmonic mode-locking of erbium-doped fiber laser at 40 GHz using a loss-modulated Fabry-Pe/spl acute/rot laser diode

Rational harmonic mode-locking of an Erbium-doped fiber ring laser (EDFL) at repetition frequency of 40 GHz is demonstrated by using a purely loss-modulated Fabry-Pe/spl acute/rot laser diode (FPLD) at 1 GHz. The FPLD is neither lasing nor gain-switching, which requires a threshold modulation power of 18 dBm to initiate harmonic mode-locking of the EDFL. After chirp compensation, the nearly transform-limited pulsewidth and spectral linewidth of 3 ps and 1.3 nm are obtained at repetition frequency of 40 GHz, which corresponds to a time-bandwidth product of 0.31. The EDFL gradually evolves from harmonic mode-locking to injection-locking mode as the FPLD changes from loss-modulation to gain-switching mode by increasing its dc driving current.     

Residual Chromatic-Dispersion Monitoring and Dynamic Compensation in 40-Gb/s Systems

A dynamic chromatic-dispersion-compensation system is implemented with a residual chromatic-dispersion monitoring module based on self-frequency shift effects in a semiconductor optical amplifier. Experimental results show that the compensation range of the system is 100 ps/nm and the residual chromatic dispersion of the transmission link is less than 5 ps/nm.     

A 40-Gb/s clock and data recovery circuit in 0.18-/spl mu/m CMOS technology

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-/spl mu/m CMOS technology, the circuit produces a clock jitter of 0.9 ps/sub rms/ and 9.67 ps/sub pp/ with a PRBS of 2/sup 31/-1 while consuming 144 mW from a 2-V supply.     

Fully electrical 40-Gb/s TDM system prototype based on InP HEMTdigital IC technologies

This paper presents a fully electrical 40-Gb/s time-division-multiplexing (TDM) system prototype transmitter and receiver. The input and output interface of the prototype are four-channel 10-Gb/s signals. The prototype can be mounted on a 300-mm-height rack and offers stable 40-Gb/s operation with a single power supply voltage. InP high-electron mobility transistor (HEMT) digital IC's perform 40-Gb/s multiplexing/demultiplexing and regeneration. In the receiver prototype, unitraveling-carrier photodiode (UTC-PD) generates 1 V_pp output and directly drives the InP HEMT decision circuit (DEC) without any need for an electronic amplifier. A clock recovery circuit recovers a 40-GHz clock with jitter of 220 fs_pp from a 40-Gb/s nonreturn-to-zero (NRZ) optical input. The tolerable dispersion range of the prototype within a 1-dB penalty from the receiver sensitivity at zero-dispersion is as wide as 95 ps/nm, and the clock phase margin is wider than 70° over almost all the tolerable dispersion range. A 100-km-long transmission experiment was performed using the prototype. A high receiver sensitivity [-25.1 dBm for NRZ (2⁷-1) pseudorandom binary sequence (PRBS)] was obtained after the transmission. The 40-Gb/s regeneration of the InP DEC suppressed the deviation in sensitivity among output channels to only 0.3 dB. In addition, four-channel 40-Gb/s wavelength-division-multiplexing (WDM) transmission was successfully performed     

Transmission performance analysis of 8/spl times/10 Gb/s WDM signals using cascaded SOAs due to signal wavelength displacement

We have analyzed the transmission performance of 8/spl times/10 Gb/s wavelength division multiplexing (WDM) signals due to crosstalk in cascaded conventional semiconductor optical amplifiers (SOAs). Using two different methods, the crosstalk over the whole gain bandwidth in SOAs is calculated to be 2-5 dB lower for the positive detuning. Then, transmission performance of 8/spl times/10 Gb/s WDM signals up to 6/spl times/40 km span in terms of receiver sensitivity is estimated over various transmission distances using cascaded SOAs for the positive signal wavelength displacement of 30, 40, and 50 nm. Especially for 50 nm detuning, transmission performances with and without using a reservoir channel are similar to each other. Our results suggest that SOAs can be used as an optical amplifier for displacement larger than 50 nm without using the reservoir channel.     

2/spl times/40 Gbit/s RZ-DQPSK transmission with tunable chromatic dispersion compensation in 263 km fibre link

2/spl times/40 Gbit/s RZ-DQPSK transmission over a 263 km fibre link with back-to-back receiver sensitivity of -27.5 dBm and Q factor >20 dB is demonstrated. The experiment demonstrates sufficient resilience against nonlinear phase noise and band limitation in a 40 Gbit/s WDM DEMUX with Q=17.5 dB.     

40-Gb/s NRZ wavelength conversion with 3R regeneration using an EA modulator and SOA polarization-discriminating delay interferometer

We propose and demonstrate, for the first time, to our knowledge, a 40-Gb/s nonreturn-to-zero wavelength converter with 3R regeneration based on an electroabsorption modulator and semiconductor optical amplifier polarization-discriminating delay interferometer. The results show that the root mean square timing jitter and optical signal-to-noise ratio (OSNR) of the regenerated signal are kept to 0.68 ps and higher than 40 dB/0.1 nm, respectively. In addition, the measured receiver sensitivity (BER=10/sup -9/) is improved from -19 to -25.2 dBm at the input OSNR of 26 dB/0.1 nm.     

A 20-GHz phase-locked loop for 40-gb/s serializing transmitter in 0.13-/spl mu/m CMOS

A 20-GHz phase-locked loop with 4.9 ps/sub pp//0.65 ps/sub rms/ jitter and -113.5 dBc/Hz phase noise at 10-MHz offset is presented. A half-duty sampled-feedforward loop filter that simply replaces the resistor with a switch and an inverter suppresses the reference spur down to -44.0 dBc. A design iteration procedure is outlined that minimizes the phase noise of a negative-g/sub m/ oscillator with a coupled microstrip resonator. Static frequency dividers made of pulsed latches operate faster than those made of flip-flops and achieve near 2:1 frequency range. The phase-locked loop fabricated in a 0.13-/spl mu/m CMOS operates from 17.6 to 19.4GHz and dissipates 480mW.     

Dynamic PMD compensator for 40 Gb/s PM-DQPSK system

The adaptive polarization mode dispersion(PMD) compensation in high-speed transmission system has become more and more necessary for the link PMD causing strong signal distortions.A dynamic adaptive PMD compensator in 40 Gb/s polar-multiplex differential quadrature phase shift keying(PM-DQPSK) system is reported.Experimental results show that the PMD compensator can track the average polarization state variation at 65 rad/s without any lost of the optimum tracking.The 1st-order PMD compensation is demonstrated experimentally,and the compensator can increase the maximal tolerable PMD value by 26 ps from 17 ps to 43 ps in an optical transmission system.     

Low insertion loss and low dispersion penalty InGaAsP quantum-well high-speed electroabsorption modulator for 40-Gb/s very-short-reach, long-reach, and long-haul applications

We present a metal-organic-chemical-vapor-deposition-grown low-optical-insertion-loss InGaAsP/InP multiple-quantum-well electroabsorption modulator (EAM), suitable for both nonreturn-to-zero (NRZ) and return-to-zero (RZ) applications. The EAM exhibits a dynamic (RF) extinction ratio of 11.5 dB at 1550 nm for 3 Vp-p drive under 40-Gb/s modulation. The optical insertion loss of the modulator in the on-state is -5.2 dB at 1550 nm. In addition, the EAM also exhibits a 3-dB small-signal response (S21) of greater than 38 GHz, allowing it to be used in both 40-Gb/s NRZ and 10-Gb/s RZ applications. The dispersion penalty at 40 Gb/s is measured to be 1.2 dB over /spl plusmn/40 ps/nm of chromatic dispersion. Finally, we demonstrate 40-Gb/s transmission performance over 85 km and 700 km.     

A 3.0 V 40 Mb/s hard disk drive read channel IC

This paper presents a high performance low power BiCMOS mixed signal ASIC that integrates all the electronics required by a hard disk drive (HDD) read channel. The IC includes the automatic gain control (AGC) circuit, a programmable continuous-time filter, two pulse qualifiers, the servo demodulator, the time base generator, the data synchronizer, and the encoder/decoder. Constant density recording with data rates between 14 and 40 Mb/s in 1,7 Run Length Limited (RLL) format and embedded 4-burst servo are supported. All the chip's specifications are guaranteed for supply voltages ranging from 3.0-5.5 V. Programming and testing are achieved via a 3-terminal bi-directional serial interface and internal registers. Nominal power dissipation at 3.0 V supply and 40 Mb/s data rate is 360 mW. Pulse pairing and write data jitter, two key performance parameters, each measured less than 300 ps     

All-optical payload envelope detection for variable length 40-gb/s optically labeled packets

We demonstrate a new technique to all-optically identify the precise temporal locations and durations of the payloads of optical packets consisting of a variable length 40-Gb/s return-to-zero payload and 10-Gb/s nonreturn-to-zero label. The all-optically generated payload envelope signal can be used to erase the original optical label and rewrite a new label. The recovered payload envelope has 300-ps rise time and edge root-mean-square average jitter of 30 ps over a 10-dB dynamic range of input optical packet power. These numbers indicate that this technique enables the use of very short guard bands between payloads. The technique is demonstrated using optical semiconductor devices that are straightforward to monolithically integrate on a single chip.     

对40 Gb/s OTDM系统中光纤光栅色散补偿器进行偏振模色散补偿的研究

改变光纤光栅紫外曝光系统 ,在相位掩模板后插入一个旋转装置 ,使得光纤在制作过程中可以进行某种旋转。通过这种方法制作的光纤光栅偏振模色散减小到平均差分群时延 (DGD)约为 0 2ps,而没加旋转制作的光纤光栅平均DGD约为 18 2 ps。采用两个这种低偏振模色散 (PMD)的光纤布拉格光栅 (FBG) ,成功地在 4 0Gb/s光时分复用 (OTDM)系统中补偿了约 2 0 4 0 ps的色散 ,该系统在经过 12 2km普通单模光纤传输后 ,未发现PMD的影响 ,传输功率代价小于 1 4dB。