变采样周期网络控制系统的H∞控制

时延以及数据包丢失是导致网络控制系统性能降低的重要原因.利用既是时钟驱动又是事件驱动的传感器,可以使时延与采样周期具有相同的长度,这样降低了建模随机时延的保守性.通过把具有时变采样周期的网络控制系统建模为切换系统,并利用线性矩阵不等式,本文给出了保证系统渐进稳定的充分条件,同时设计了系统的H∞控制器,仿真结果表明了本文所提出的变采样周期方法的有效性.     

被动变采样周期网络控制系统的H∞控制器设计

本文研究了具有被动变采样周期网络控制系统的H∞控制器设计问题。提出了基于采样周期切换的方法（采样周期在有限集合内切换），并利用该方法将具有时变采样周期及时延的网络控制系统建模为切换系统。在此基础上，通过求解满足一组线性矩阵不等式约束的多目标优化问题，研究了网络控制系统的H∞控制器设计方法。仿真结果验证了基于采样周期切换的H∞控制器设计方法的有效性。     

多速率预测控制系统最优采样周期的研究

随着社会工业的不断发展,在复杂的化工过程中越来越多地开始采用多速率控制系统,而采样周期是这种数字控制系统中的重要参数,对系统有着多方面的影响。目前基于采样周期的选取大多数是根据传统的实际经验来确定选取范围,还没有1种方法能够较准确的找到系统所需求的最适合的采样周期。本文针对一类多输入——多输出的系统,采用动态矩阵预测控制算法,通过建立1个简单的两输入——两输出系统的输入多速率模型,进一步推导出了多输入——多输出系统基于动态矩阵的通用输入多速率模型;采用经典的优化算法——遗传算法,对这种输入多速率下采样周期进行了优化选取,并针对一类双入双出的快慢耦合系统进行了仿真,在基本采样周期T一定的条件下,找到了使得系统控制性能最优的各个输入采样周期,得到最优控制效果(积分平方误差),对应的两个输入采样周期分别为基本采样周期的5倍和1倍,并将其与单速率下的控制性能进行了比较。结果表明,本文提出的这种方法可以有效的得到系统最优的采样周期,并且,对于这种病态耦合系统,在采样周期的适当选取下,输入多速率下系统的稳定性及综合控制性能优于单速率控制系统。     

面向密码流处理器的AES算法软件流水实现方法

针对轮函数在分组密码实现过程中耗时过长的问题,提出了面向可重构密码流处理器（RCSP）的高级加密标准（AES）算法软件流水实现方法。该方法将轮函数操作划分为若干流水段,不同流水段对应不同的并行密码资源,通过并行执行多个轮函数的不同流水段,从而开发指令级并行性提高轮函数执行速度,进而提升分组密码的执行性能。在RCSP的单簇、双簇和四簇运算资源下分析了AES算法的流水线划分过程和软件流水映射方法,实验结果表明,该软件流水实现方法使得单分组或多分组不同数据分块的操作并行执行,不仅能够提升单分组串行执行性能,还能够通过开发分组间的并行性来提高多分组并行执行性能。     

具有时变采样周期的网络控制系统的H∞控制

研究了具有时变采样周期的网络控制系统的H∞鲁棒控制器设计问题．提出了基于变采样周期的切换方法（采样周期在有限集合内切换），并利用该方法将存在时变采样周期、长时延以及丢包的网络控制系统建模为切换系统．在此基础上，通过把一个非凸的可行性问题转化为受线性矩阵不等式约束的多目标优化问题，研究了网络控制系统的H∞控制器设计方法．仿真结果验证了基于采样周期切换的H∞控制器设计方法的有效性．     

基于主动变采样周期方法的网络控制系统的H∞控制器设计

利用主动变采样周期方法, 本文研究了具有时延及丢包的网络控制系统的 H∞ 控制器设计问题, 其中采样周期在一个有限集合内切换. 提出了一个新的线性估计方法以补偿丢包的负面影响, 并利用多目标优化方法设计系统的 H∞ 控制器. 仿真结果表明了主动变采样周期方法及基于线性估计的丢包补偿方法的有效性.     

反馈控制实时调度中采样周期的研究

以CPU资源调度为典型应用背景，研究并分析了采样周期对反馈控制实时调度和一般数字控制系统性能影响的差异，通过仿真实验得出采样周期的选择对反馈控制实时调度性能影响规律，提出了采样周期的选择方法。对于平均执行时间难以预测的任务集，提出一种可变采样周期的有效解决方案。     

变采样网络控制系统的最优保性能控制

研究了一类不确定时延网络控制系统的最优保性能控制问题.针对线性时不变控制对象,控制器和控制对象采用时间-事件驱动,系统成为变采样网络控制系统,考虑在不确定时延小于或者等于一个变采样周期时,基于动态输出反馈对变采样网络控制系统进行建模,利用线性矩阵不等式研究了系统的保性能控制,并设计了保性能控制率和最优保性能控制率,最后给出实例表明在最优保性能控制率的控制下系统稳定.     

可编程控制器数据采样特殊性问题讨论

可编程控制器采样周期由扫描周期决定,在上位机和可编程控制器组成控制系统中,上位机以通讯方式获得可编程控制器的采样数据周期由查询采样数据的间隔时间所决定,主要从可编程控制器逻辑编程和上位机采样数据处理两个方面入手,提出解决上位机获得采样周期较短的实时采样数据一种方法。     

一种基于网络控制的在线时延估算算法

针对模型中网络时延的时变特性,提出了一种基于ControlNet的不需要传感器-控制器及控制器-执行器时钟同步的在线时延估算算法,根据估算得到的时延确定LQR控制器中的控制参数,并进行了仿真实验,结果表明有效地利用了系统资源,提高了控制回路的采样速率,从而提高了控制系统性能。     

基于双率采样的智能车辆弯道轨迹跟踪控制

本文研究在双率采样下智能车辆弯道轨迹跟踪问题.首先,针对车辆车道保持的转向控制,建立相对路面误差的侧向动力学模型.其次,假设系统状态变量被分为两个子向量并分别由两类传感器以不同的采样周期采样,针对这类双率采样系统,充分考虑这两类传感器的采样时刻特征,设计一类基于采样时刻的切换控制器.然后,利用输入时滞方法,将最终的闭环系统建模为带有两个模态的切换时滞系统,并以线性矩阵不等式(LMI)形式给出闭环系统指数稳定性条件和切换控制器的设计方法.最后,在Matlab/Simulink环境下对汽车模型的路径跟踪控制进行仿真,验证本文所提方法的有效性,并与单率采样方法进行比较,说明本文方法相比于单率采样方法的优势.     

Non-preemptible last section assignment for reducing feedback latency in real-time control systems

A real-time control system design procedure consists of the controller design stage and the implementation stage. In the controller design stage, various digital control theories are used with assumptions, such as synchronous sampling, no sampling jitter and negligible feedback latency (latency from sensing to actuation). However, in the implementation stage, multiple control tasks are usually scheduled on a processor, which creates a finite sampling period, varying feedback latency and sampling jitter, and therefore the controller's performance is degraded. In this article, we investigate the relationship between control performance and timing parameters. In the course of this investigation, we found that the feedback latency is the dominant factor affecting control performance. In addition, we propose a rate monotonic (RM) scheduler with non-preemptible last section algorithm, which can reduce the feedback latency considerably. The proposed algorithm provides better control performance than a preemptive RM scheduler, in most cases. The effectiveness of the proposed algorithm is shown in illustrative examples.     

网络传输迟延与丢包的补偿及系统稳定性分析

针对网络传输在控制系统中引发的问题,提出在控制器节点采用针对迟延和丢包的补偿估计器．以提高控制系统的性能。当迟延小于一个采样周期且数据包传输率已定时,将包含该补偿估计器的网络控制系统（CEDPNCS）,描述为具有两个事件的异步动态系统,并推导出保证系统稳定的时变双线性矩阵不等式．仿真结果表明．所提出的方法能有效提高控制系统的性能．     

Time delay and sampling rate effect on dual-stage servo control performance

Dual-stage servo control loops are modeled for hard disk drives (HDDs) with the consideration of time delay which is due to the time taken for position error signal measurement and controller computing. The time delays are involved in controller design and the closed servo control loop is investigated to show the effects of the time delay on servo control performance. The studied actuation system is a PZT milliactuator based dual-stage servo system. The delay time within and over the sampling interval is separately considered for 62.5 kHz sampling rate. To show the effect of sampling rate on servo control performance, a control system designed with 40 kHz sampling rate is also studied. As a result, significant improvement of servo performance is attained with this increased sampling rate and a reasonable time delay for the dual-stage actuation system.     

The JRPM system for dynamically parallelizing sequential Java programs

As instruction-level parallelism with a single thread of control approaches its performance limits, designers must find other architectural improvements to speed up program execution. The Java runtime parallelizing machine (JRPM) system takes advantage of recent developments to enable a new approach to automatic parallelization. JRPM can exploit thread-level parallelism with minimal programmer effort.     

Coarse-grained thread pipelining: a speculative parallel executionmodel for shared-memory multiprocessors

This paper presents a new parallelization model, called coarse-grained thread pipelining, for exploiting speculative coarse-grained parallelism from general-purpose application programs in shared-memory multiprocessor systems. This parallelization model, which is based on the fine-grained thread pipelining model proposed for the superthreaded architecture, allows concurrent execution of loop iterations in a pipelined fashion with runtime data-dependence checking and control speculation. The speculative execution combined with the runtime dependence checking allows the parallelization of a variety of program constructs that cannot be parallelized with existing runtime parallelization algorithms. The pipelined execution of loop iterations in this new technique results in lower parallelization overhead than in other existing techniques. We evaluated the performance of this new model using some real applications and a synthetic benchmark. These experiments show that programs with a sufficiently large grain size compared to the parallelization overhead obtain significant speedup using this model. The results from the synthetic benchmark provide a means for estimating the performance that can be obtained from application programs that will be parallelized with this model. The library routines developed for this thread pipelining model are also useful for evaluating the correctness of the codes generated by the superthreaded compiler and in debugging and verifying the simulator for the superthreaded processor     

Many task computing for orthologous genes identification in protozoan genomes using Hydra

One of the main advantages of using a scientific workflow management system (SWfMS) is to orchestrate data flows among scientific activities and register provenance of the whole workflow execution. Nevertheless, the execution control of distributed activities in high performance computing environments by SWfMS presents challenges such as steering control and provenance gathering. Such challenges may become a complex task to be accomplished in bioinformatics experiments, particularly in Many Task Computing scenarios. This paper presents a data parallelism solution for a bioinformatics experiment supported by Hydra, a middleware that bridges SWfMS and high performance computing to enable workflow parallelization with provenance gathering. Hydra Many Task Computing parallelization strategies can be registered and reused. Using Hydra, provenance may also be uniformly gathered. We have evaluated Hydra using an Orthologous Gene Identification workflow. Experimental results show that a systematic approach for distributing parallel activities is viable, sparing scientist time and diminishing operational errors, with the additional benefits of distributed provenance support. Copyright © 2011 John Wiley & Sons, Ltd.     

论微机控制系统的采样周期

对微机控制系统的采样周期进行了研究，以一典型控制系统为例，从理论上分析了采样周期对系统的稳定性、动态品质、抗干扰能力及数字PID控制作用的影响，并指出过小的采样周期会使最小相位系统的性质发生改变。     

Optimal sampling-rates and tracking properties of digital LQ and LQG tracking controllers for systems with an exogenous component and costs associated to sampling

In this paper it is shown that if costs are associated to sampling operations which are added to a performance criterion, the minimization of this new performance criterion results in a controller operated at an optimal sampling rate. This, under the assumptions that the system is periodically sampled, the applied control is kept fixed between every two sampling instances and some technical conditions are met. In case the considered planning horizon in the performance criterion is finite an algorithm is devised which calculates in a finite number of steps the optimal sampling period. It is shown that the technical conditions mentioned above are satisfied by the finite planning horizon time-varying LQG tracking problem. Since stability is a major requirement in controller design we also consider the case of an infinite planning horizon. This analysis is focused on the time-invariant digital LQ tracking problem. Given some mild regularity conditions a numerical algorithm is presented that approximates the optimal solution within any prespecified error norm. It is shown that also in this case an optimal sampling-rate exists. The algorithm for determining the optimal sampling period if the planning horizon is finite is illustrated in an economic example.     

Control of sampled-data systems with variable sampling rate

This paper addresses stability and performance of sampled-data systems with variable sampling rate, where the change between sampling rates is decided by a scheduler. A motivational example is presented, where a stable continuous time system is controlled with two sampling rates. It is shown that the resulting system could be unstable when the sampling changes between these two rates, although each individual closed-loop system is stable under the designed controller that minimizes the same continuous loss function. Two solutions are presented in this paper. The first solution is to impose restrictions on switching sequences such that only stable sequences are chosen. The second solution presented is more general, where a piecewise constant state feedback control law is designed which guarantees stability for all possible variations of sampling rate. Furthermore, the performance defined by a continuous time quadratic cost function for the sampled-data system with variable sampling rate can be optimized using the proposed synthesis method.