Analytical solutions for the breakdown voltages of punched-through diodes having curved junction boundaries at the edges

Analytical expressions are derived for the breakdown voltages of punched-through diodes having a plane structure terminated with cylindrical and spherical curved boundaries at the edges, through the use of suitable approximations for the electric field in the depletion layer. The expressions derived include both p⁺-i-n⁺and p⁺-p-n⁺(or p⁺-n-n⁺) types and are given in terms of the middle-region (i-layer or p-layer) width, the radius of curvature of the junction edge, the punch-through voltage, and the plane parallel breakdown voltage of p⁺-i-n⁺diodes. The results obtained include a correlation between the middle-region (p-layer) width and the width of the depletion layer in the curved portions of the junction when the applied reverse bias across the diode is just sufficient so that punchthrough takes in the portions where the junction is plane parallel. These results are made use of in the breakdown voltage calculations.     

Amorphous silicon phototransistor on a glass substrate

An amorphous silicon n⁺-i-p⁺-i-n⁺thin-film phototransistor was made on a glass substrate. The p⁺base is very thin (∼ 200 Å) compared with 2000 to 5000 Å of the collector i-layer. Therefore, the emitter current which is induced from the photogenerated flux in the collector i-layer is very high. In addition, hole lifetime (minority carrier in the emitter) and transit time are very short, the device possesses fast rise time and fall time of 30 µs, which is mainly governed by the junction capacitance-resistance charging effect and strays.     

Impact ionization rates in (100)Al0.48In0.52As

Impact ionization rates for electrons and holes in (100) Al_0.48In_0.52As were determined from photomultiplication measurements using AlInAs/GaInAs p⁺-i-n diodes grown by metalorganic vapor phase epitaxy (MOVPE). The impact ionization-rate ratio was derived as being 2.0~3.5 over the electric field range from 400 to 650 kV/cm. Ionization rates were found to be smaller than those previously reported. These results could be useful for designing AlInAs/GaInAs superlattice avalanche photodiodes with an electron-initiated configuration     

A study of the conversion efficiency limit of p+-i-n+silicon solar cells in concentrated sunlight

The conversion efficiency limit of p⁺-i-n⁺silicon solar cells in concentrated sunlight is explored with numerical simulations of an idealized p⁺-i-n⁺cell having field-induced junctions. Conversion efficiencies greater than 30 percent are calculated for this cell operating in sunlight concentrated 1000 times. The relative importance of bulk and surface recombination in limiting the cell conversion efficiency is illustrated for operation in 1 to 1000 suns. For surface recombination velocities below 100 cm/s, it is shown that bulk recombination losses limit the cell performance rather than recombination losses occurring in the p⁺or n⁺regions. The results show that Auger recombination in the bulk region will limit ultimately the cell conversion efficiency.     

DC characterization of fully ion-implanted p-n junctions intosemi-insulating InP

The forward and reverse characteristics of p⁺-n junctions made by Mg and Si implantation and rapid thermal annealing into Fe-doped semi-insulating InP are described. The effects of the Si dose for obtaining the n-type region, the use of P co-implantation for obtaining the p⁺ region, and the annealing time are studied. The dominant conduction mechanism at forward bias was found to be recombination in the space-charge region, with ideality factors of n=2 down to 198 K, and temperature dependence with an activation energy of 0.76 eV. The reverse characteristics presented junction breakdown at voltages around -20 V, and were accurately described by a thermally-activated trap-assisted tunneling mechanism. The energy of the corresponding trap, obtained by the fitting of the experimental characteristics, was 0.6 eV, and its origin was tentatively ascribed to the Fe deep acceptor present in semi-insulating InP     

Epitaxial silicon solar cells with uniformly doped layer

Solar cell structures have been prepared both by successive deposition of p-type and n-type silicon layers on p⁺-type single-crystal silicon. Impurities are uniformly doped at epitaxial layers. Efficiency of 9.0 percent with the epitaxial layer junction structure and 12.8 percent with the diffused 0.3-μm junction depth structure have been achieved.     

Fully implanted InP JFET with an abrupt p+-n junction

We report the first fully implanted InP junction field-effect transistor (JFET) with an abrupt p⁺-n junction. The device was made on a semi-insulating InP substrate with Si⁺⁺implant for the n-channel and Be/P co-implant for the p⁺-region. A novel self-aligned process was used to reduce the gate-source spacing and thus minimize the series resistance. Good pinch-off characteristics and very low gate leakage current were obtained. The extrinsic transconductance is approximately 40 mS/mm for a gate length of 5 µm and a channel doping of 6 × 10¹⁶/cm³.     

Power-impedance-frequency limitations of IMPATT oscillators calculated from a scaling approximation

The obtainable CW power of silicon IMPATT oscillators, as a function of frequency, is calculated by scaling from reference results. The analysis differs from previous treatments in that the microwave circuit impedance limitation, as observed experimentally, is utilized simultaneously with thermal impedance limitations to uniquely determine device diameter, operating currents, and output power. Results are presented for single and multiple (parallel) units on copper and diamond mounting studs, and for both single (p⁺-n-n⁺) and double-drift-region (p⁺-p-n-n⁺) structures. Obtainable power falls off essentially as 1/f until an ultimate (nonthermal) space-charge-limited current density is reached. Beyond this point the obtainable power varies as f^-2.14. The calculated results on single-drift-region structures are in agreement with experimental observations over the range of frequencies from 13 to 55 GHz, and the analysis predicts an obtainable power of 300 mW at 110 GHz for a double-drift-region structure with 10 percent conversion efficiency.     

High-efficiency ion-implanted silicon solar cells

The development of solar cells with AM1 coversion efficiency of 18 percent is reported. The cells comprise an n⁺-p-p⁺structure fabricated from float zone silicon having resistivity of 0.3 Ω . cm. The n⁺and p⁺regions are formed by low energy ion implantation and thermal annealing. An important feature of cell fabrication is the growth of SiO2passivation for reduction of surface recombination velocity. Details of both cell fabrication and testing are reported.     

A modified GaAs IMPATT structure for high-efficiency operation

A p⁺-n⁽⁺⁾-n-n⁺just punchthrough IMPATT structure is proposed and analyzed. This high-low junction structure differs from the Read structure in that the carrier concentration in the n-layer is high enough that the breakdown and punchthrough occur at the same time; yet it differs with the regular p⁺-n junction structure in that an additional n⁽⁺⁾-layer with prescribed carrier concentration and layer thickness is present. Tradeoffs between the efficiency and noise of this high-low junction IMPATT are presented and compared to the case of a conventional p-n junction IMPATT. It is shown that either the efficiency or noise performance can be improved, although one at the expense of the other. As an example, the maximum efficiency of a high-low junction IMPATT is improved from about 23 to 30 percent at the expense of a degradation in noise performance of 7 dB. On the other hand, the noise of an X-band diode can be improved by 6 dB with a degradation in efficiency from 23 to 12 percent. This structure should be useful for high-efficiency high-power applications where the noise specifications can be relaxed, or as local oscillators where the noise performance is important.     

Analysis of a technology for CZ bifacial solar cells

A bifacial cell technology for Cz Si and evaporated contacts is presented. A p⁺nn⁺ structure on high resistivity material gives 17.7% for n⁺ side illumination and 15.2% for p ⁺ side illumination. Cell performance is analyzed by fitting experimental measurements with PC1D. Analysis shows that p⁺ layer puts a limit to cell performance, mainly due to a high surface recombination velocity. The boron depleted zone near the surface also enhances recombination, but its effect can be reduced by performing a boron etch-back step in the process. Cells with boron etch-back give higher short-circuit current and a reduction of open-circuit voltage of around 10 mV. These results are consistent with the PC1D model     

Planar, fully ion-implanted InP junction FETs with anitride-registered gate metallization

A planar, fully ion-implanted indium phosphide (InP) junction FET (JFET) fabrication process is described, which utilizes n⁺ source-drain implantation, Be and Be/P p⁺ gate implantation, AuZn/Ni/TiW/Au nitride-registered gate metallization, and proximity rapid thermal annealing. Devices fabricated with this approach exhibited a maximum transconductance of 140 mS/mm, which is believed to be the highest reported for InP JFETs     

20-GHz high-power GaAs DDR-IMPATT diodes with a p+-p-n-n+structure

GaAs DDR (double-drift-region)-IMPATT diodes have been made by using epitaxial wafers with a p⁺-p-n-n⁺structure, which was made by successive liquid-phase epitaxy of p⁺, p, and n layers on n⁺substrate in one heat cycle. On the diodes with copper heat sink, the maximum CW output power of 1.2 W was obtained at 21 GHz with the efficiency of 15.6 percent.     

Ultrathin, high-efficiency solar cells made from GaAs films prepared by the CLEFT Process

Solar cells with conversion efficiencies as high as 17% at AM1 have been fabricated from single-crystal 10-µm-thick GaAs films prepared by the CLEFT process. These cells are the first devices to employ CLEFT films. In making a cell, a GaAs film with an n⁺/p/p⁺shallow-homojunction structure is grown by vapor-phase epitaxy on a specially masked single-crystal GaAs substrate, then transferred to a glass substrate that serves as the cell cover glass. The GaAs substrate can be reused repeatedly for preparing additional CLEFT films.     

High-performance InGaAs junction field-effect transistor with P/Beco-implanted gate

InGaAs junction field-effect transistors (JFETs) are fabricated in metalorganic chemical-vapor-deposition (MOCVD)-grown n-InGaAs and semi-insulating Fe:InP layers on n⁺-InP substrate with a P/Be co-implanted p⁺ self-aligned gate. The device exhibits a transconductance of 245 mS/mm (intrinsic transconductance of 275 mS/mm) at zero gate bias and good pinch-off behavior for a gate length of 0.5 μm. The effective electron velocity is deduced to be 2.8×10⁷ cm/s, equal to the theoretical prediction     

Design considerations of low-noise high-efficiency silicon IMPATT diodes

The noise and efficiency of p⁺-n1-n2-n⁺and n⁺-p1- p2-p⁺high-low silicon IMPATT diodes have been studied as a function of doping ratio n1/n2or p1/p2. In contrast to GaAs IMPATT diodes whose efficiency can be improved with some degradation of noise performance, both the efficiency and noise of Si IMPATT diodes can be improved. As an example, for a 6-GHz silicon n⁺-p1-p2-p⁺IMPATT structure with a doping ratio of 10, the efficiency is 21 percent and the incremental noise as compared to a uniformly doped structure is about -6 dB. These results indicate that silicon high-low structures can compete favorably with GaAs structures in both efficiency and noise performances.     

100 Å-thick tunnel junction by double impurity doping liquid phase epitaxy for V-band TUNNETT oscillation

The tunnel injection transit time (TUNNETT) diodes with p⁺p⁺n⁺n⁻n⁺ structure were fabricated by liquid phase epitaxy (LPE). About 100 Å tunnel junction (p⁺n⁺) was successfully prepared by the double impurity diffusion of Ge and S during LPE growth. Continuous wave (CW) oscillation was realized at 51.520 GHz in the V-band cavity with the phase noise of −60 dBc/Hz at 1 kHz bandwidth.     

n+/p+ Gate Bulk FinFETs With Locally Separated Channel Structure for Sub-50-nm DRAM Cell Transistors

We proposed a new p⁺/n⁺ poly-Si gate bulk fin-type field-effect transistor that has two channel fins separated locally by a shallow trench filled with oxide or p⁺ polygate. Key device characteristics were investigated by changing the n⁺ poly-Si gate length La, the material filling the trench, and the width and length of the trench at a given gate length L_g. It was shown that the trench filled with p⁺ poly-Si gate should not be contacted with the source/drain diffusion region to achieve an excellent I_on/I_off (> 1010) that is suitable for sub-50-nm dynamic random access memory cell transistors. Based on the aforementioned device structure, we designed reasonable Ls/Lg and channel fin width W_cfin at given L_g 's of 30, 40, and 50 nm.     

A low-voltage high-speed silicon photodiode with buried isolation region for short-haul optical-fiber communications

A new epitaxial silicon p-i-n photodiode has been developed for short-haul optical-fiber communications that can be operated at biases as low as 4 V. The device has a heavily doped 5-µm-thick p⁺⁺isolation-region between the p⁺substrate and the π-epitaxial layer. Fast rise and fall times (2 ns), and low leakage current (40 pA) result from the recombination and trapping of the minority-carrier electrons in the substrate. Experimental results on such an n⁺-π-p⁺⁺-p⁺device with 1.1-mm²photosensitive area and 25-µm epi-layer thickness show quantum efficiency of 80 percent at 825-nm wavelength.