A tri-band, 2-RX MIMO, 1-TX TD-LTE CMOS transceiver

In this work, a tri-band (Band 39: 1880–1920 MHz, Band 40: 2300–2400 MHz, and Band 38: 2570–2620 MHz), 2-receiver (RX) multiple-in-multiple-out (MIMO), 1-transmitter (TX) TD-LTE (Time Division Long Term Evolution) CMOS transceiver is presented and fabricated in 0.13-μm CMOS technology. The continuous-time delta–sigma A/D converters (CT ΔΣ ADCs) are directly coupled to the RX front-end outputs to achieve low power. With proper gain allocation and a novel carrier leakage calibration, the TX section ensures at least –40 dBc carrier leakage suppression over 86-dB gain range. The transceiver dissipates maximum 171 mW at 2-RX MIMO mode and 183 mW at 1-TX maximum gain mode. To the best of our knowledge, this is the first research paper on fully integrated commercial TD-LTE transceiver.     

新型北斗用户机射频模块设计

为减小北斗用户机的体积,降低终端成本,缩短终端系统调试时间,文中采用北斗卫星导航系统专用射频芯片,设计了一款新型的北斗用户机模块。该模块体积仅为27mm×19mm。调试后的测试结果为：接收通道噪声系数小于4．5dB,AGC（自动增益控制）范围大于55dB,中频输出幅度为峰峰值1V,输入驻波比小于1．5;发射通道功率调整范围达到-10dBm～5dBm,输出1dB压缩点大于10dBm,本振抑制大于30dB,本振相位噪声误差小于0．9°。测试结果表明射频模块性能全部满足整机要求。     

An ultra-low-power RF transceiver for WBANs in medical applications

A 2.4 GHz ultra-low-power RF transceiver with a 900 MHz auxiliary wake-up link for wireless body area networks(WBANs)in medical applications is presented.The RF transceiver with an asymmetric architecture is proposed to achieve high energy efficiency according to the asymmetric communication in WBANs.The transceiver consists of a main receiver(RX)with an ultra-low-power free-running ring oscillator and a high speed main transmitter(TX)with fast lock-in PLL.A passive wake-up receiver(WuRx)for wake-up function with a high power conversion efficiency(PCE)CMOS rectifier is designed to offer the sensor node the capability of work-on-demand with zero standby power.The chip is implemented in a 0.18μm CMOS process.Its core area is 1.6 mm~2. The main RX achieves a sensitivity of-55 dBm at a 100 kbps OOK data rate while consuming just 210μA current from the 1 V power supply.The main TX achieves +3 dBm output power with a 4 Mbps/500 kbps/200 kbps data rate for OOK/4 FSK/2 FSK modulation and dissipates 3.25 mA/6.5 mA/6.5 mA current from a 1.8 V power supply. The minimum detectable RF input energy for the wake-up RX is-15 dBm and the PCE is more than 25%.     

Design and analysis of TX/RX dual microstrip antenna using FDTD at Ku-band

A TX/RX dual microstrip 8/spl times/4 array antenna for satellite communication is designed, fabricated and measured and its element characteristics are analysed using finite difference time domain (FDTD) method. TX/RX frequency ranges are 14.0-14.5 GHz, 11.7-12.75 GHz, respectively, and vertical and horizontal polarisations are used for TX and RX. This antenna uses microstrip direct feeding for RX and aperture coupled stripline feeding for TX and accommodates stacked elements for a high directivity and wide impedance bandwidth. FDTD gives more accurate results because of the consideration of finite structure and two imperfect ground planes. This element has a return loss below -8 and -14 dB over the TX and RX frequency ranges and a gain of 7.5 and 8.3 dBi at the centre frequency of TX and RX. Return loss below -10 and -14 dB and a gain of 21.4 and 20.0 dBi were achieved for the TX and RX array, respectively.     

A 20-Gb/s CMOS multichannel transmitter and receiver chip set forultra-high-resolution digital displays

A multichannel transmitter (TX) and receiver (RX) chip set operating at 20 Gb/s (5 Gb/s×4 ch) has been developed by using 0.25-μm CMOS technology. To achieve multichannel data transmission and high-speed operation, the chip set features: (1) circuits for compensating the phase difference between multiple RX chips, which is due to data skew resulting from different lengths of transmission cables, and for compensating the frequency difference between the system clocks of the TX and RX chips; (2) a self-alignment phase detector with parallel output for a high-speed data-recovery circuit; and (3) a fully pipelined 8B10B encoder. At a 2.5-V power supply, the power consumption of the TX chip during 5-Gb/s operation is 500 mW and that of the RX chip is 750 mW. Four of these TX/RX chip sets can provide an aggregate bandwidth of 20 Gb/s     

采用自适应信号处理技术的低成本回波抵消器

提出了一种低成本回波抵消电路方案,采用了自适应信号处理技术,可用于连续波雷达系统中的射频收发前端,能改善载波泄漏和收发隔离度指标,从而提高接收机前端的动态范围。仿真结果表明,在采用环形器作为收发隔离器件的典型应用条件下,采用回波抵消电路后,前端可以获得57 dB以上的收发隔离度改善。该电路结构简洁、算法运算量小、载波抑制特性稳定、收敛迅速,而且对器件指标的要求并不苛刻,有利于提高系统的经济性。     

基于RX5000/TX5000的无线收发电路

RX5000和TX5000分别是RFMicro Devices公司专为小范围单向无线通信设计生产的接收器和发射器芯片。它们体积小，功耗低，价格便宜，而且性能稳定，使用方便。文中介绍了RX5000、TX5000的特点与功能，给出了以这两种器件为核心设计的无线收发电路，并对其在足球机器人无线通信系统中的应用进行了说明。     

60 GHz Single-Chip Front-End MMICs and Systems for Multi-Gb/s Wireless Communication

Single-chip 60 GHz transmitter (TX) and receiver (RX) MMICs have been designed and characterized in a 0.15mum (f_T~ 120 GHz/f _MAX> 200 GHz) GaAs mHEMT MMIC process. This paper describes the second generation of single-chip TX and RX MMICs together with work on packaging (e.g., flip-chip) and system measurements. Compared to the first generation of the designs in a commercial pHEMT technology, the MMICs presented in this paper show the same high level of integration but occupy smaller chip area and have higher gain and output power at only half the DC power consumption. The system operates with a LO signal in the range of 7-8 GHz. This LO signal is multiplied in an integrated multiply-by-eight (X8) LO multiplier chain, resulting in an IF center frequency of 2.5 GHz. Packaging and interconnects are discussed and as an alternative to wire bonding, flip-chip assembly tests are presented and discussed. System measurements are also described where bit error rate (BER) and eye diagrams are measured when the presented TX and RX MMICs transmits and receives a modulated signal. A data rate of 1.5 Gb/s with simple ASK modulation was achieved, restricted by the measurement setup rather than the TX and RX MMICs. These tests indicate that the presented MMICs are especially well suited for transmission and reception of wireless signals at data rates of several Gb/s     

A 0.13 $mu$ m CMOS Quad-Band GSM/GPRS/EDGE RF Transceiver Using a Low-Noise Fractional-N Frequency Synthesizer and Direct-Conversion Architecture

This paper presents a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS/EDGE applications which adopts a direct-conversion receiver, a direct-conversion transmitter and a fractional-N frequency synthesizer with a built-in DCXO. In the GSM mode, the transmitter delivers 4 dBm of output power with 1$^{circ}$ RMS phase error and the measured phase noise is ${-}$164.5 dBc/Hz at 20 MHz offset from a 914.8$~$MHz carrier. In the EDGE mode, the TX RMS EVM is 2.4% with a 0.5 $~$dB gain step for the overall 36 dB dynamic range. The RX NF and IIP3 are 2.7 dB/ ${-}$12 dBm for the low bands (850/900 MHz) and 3 dB/${-}$ 11 dBm for the high bands (1800/1900 MHz). This transceiver is implemented in 0.13 $mu$m CMOS technology and occupies 10.5 mm$^{2}$ . The device consumes 118 mA and 84 mA in TX and RX modes from 2.8 V, respectively and is housed in a 5$,times,$ 5 mm$^{2}$ 40-pin QFN package.      

Research on human blockage effect for indoor 26 GHz mm-wave communications

Based on 26 GHz indoor channel measurements, the blockage attenuation of human bodies was investigated. 2-ray and 4-ray human blockage models were proposed by calculation of the Vogler's multiple knife-edge diffraction field. Results show that 4-ray model fits quite well with measurement data. Human block attenuations are slightly bigger with 1 GHz than with 500 MHz bandwidth. In the blockage measurement of one person moving along the connec-tion line between the transmitter (TX) and receiver (RX), the smallest attenuation is found when the person is located at the middle of the connection line, and the biggest attenuation is observed when the person is nearest from the RX position. In the blockage measurements by multiple human bodies, the attenuation is bigger in the cases which the persons cross the TX-RX connection line with their front faces directed to the horn aperture at the RX than the cases with their lat-eral faces directed to the RX horn aperture. The blockage attenuation is larger with the increase of person numbers, about 5～8 dB more attenuation per person. The results can be used for design of mm-wave 26 GHz indoor communi-cations systems.     

A fully integrated 33.8-dBm bulk CMOS T/R switch with a negative-voltage switch controller

This paper presents a single-pole double-throw CMOS transmit/receiver (T/R) switch in a standard 0.18 μm CMOS process. The T/R switch uses 6-stacked body-floated N-MOSFETs to enhance linearity, and a negative-voltage controller integrated on a single die with the power switch cell. A complementary DICSON charge pump is employed to generate the negative voltages and three-step level shifters are used to control the switch cell. The fabricated T/R switch has P_1dB of 33.8 and 32.6 dBm at 900 and 1,800 MHz from a 2 V supply, respectively. The insertion losses of TX are 0.7 and 1.1 dB at 900 and 1,800 MHz, respectively. The isolations from TX to ANT and RX to ANT are >25 dB at both frequencies, and the return losses are >20 dB. The proposed T/R switch shows comparable or better performance compared to the previously reported T/R switches without the switch controller.     

Performance analysis of concatenated space-time coding with two transmit antennas

In this paper, we show how Alamouti's simple but useful transmit diversity scheme for two antennas can be combined with a standard outer error-correcting code to achieve a stronger concatenated space-time coding scheme. By introducing a matrix formalism that allows us to interpret the transmission channel as a rotation in an Euclidean space, it can be easily shown that this scheme with two transmit (TX) and L/sub r/ receive (RX) antennas is equivalent to a simple RX antenna setup with 2L/sub r/ RX antennas. Analytical formulas for pair error probabilities will be derived for the time and/or frequency flat fading and for the ideally interleaved Rayleigh fading channel as well as for the correlated fading channel. As a practical example, we study how the performance of a Walsh-Hadamard coded multicarrier code-division multiple-access system depends on the correlation bandwidth of the channel and the number of RX and TX antennas.     

A direct-conversion WLAN transceiver baseband with DC offset compensation and carrier leakage reduction

A dual-band direct-conversion WLAN transceiver baseband compliant with the IEEE 802.11 a/b/g standards is described.Several critical techniques for receiver DC offset compensation and transmitter carrier leakage rejection calibration are presented that enable the direct-conversion architecture to meet all WLAN specifications.The receiver baseband VGA provides 62 dB gain range with steps of 2 dB and a DC offset cancellation circuit is introduced to remove the offset from layout and self-mixing.The calibra...     

A four-channel digital signal processor in 1.2-μm CMOS withon-chip D/A and A/D conversion serving four speech channels in anew-generation subscriber line circuit

The major component for a new-generation line circuit was designed and fabricated in a 1.2-μm CMOS technology. The circuit includes digital signal processing of receive (RX) and transmit (TX) signals as well as the analog front end of four subscriber lines to a PCM (pulse code modulation) digital exchange. The device operates on a single 5-V power supply. The four-channel digital signal-processor including the analog front ends is fabricated on a 40-mm² 1.2-μm CMOS die area. The DSP functions, the RX and TX filters, the decimator, the interpolator, and the A/μ-law transcoder are included as independent data paths, one for the TX and RX filters, one for the decimator, and another for the interpolator, the digital sigma-delta modulator, and the transcoder. The on-chip analog front end contains a notch filter to cancel the 12/16-kHz payphone signal, a switched-capacitor PDM A/D and D/A converter, and smoothing filters. On the first measured samples, the signal-to-distortion ratio is measured to be 33 dB at -45 dBmo for -7 dB gain setting     

A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells

A 31.3-dBm 900-MHz bulk CMOS T/R switch with transmit (TX) and receive (RX) insertion losses of 0.5 and 1.0 dB and isolation of 29 dB is demonstrated. The switch utilizes a floating-body technique, feed-forward capacitors, and 3-stack 3.3-V MOSFETs with 0.26-mum sub-design-rule (SDR) channel length. Using these, a 28-dBm 2.4-GHz T/R switch with TX and RX insertion losses of 0.8 and 1.2 dB, and isolation of 24 dB is also demonstrated. The power handling capability is limited by an abrupt output power drop before reaching the normal 1-dB compression point. The circuits are implemented in the UMC 130-nm mixed-mode triple-well CMOS process.     

A digitally controlled oscillator system for SAW-less transmitters in cellular handsets

A complete digitally controlled oscillator (DCO) system for mobile phones is presented with a comprehensive study. The DCO is part of a single-chip fully compliant quad-band GSM transceiver realized in a 90-nm digital CMOS process. By operating the DCO at a 4 /spl times/ GSM low-band frequency followed by frequency dividers, the requirement of on-chip inductor Q and the amount of gate oxide stress are relaxed. It was found that a dynamic divider is needed for stringent TX output phase noise while a source-coupled-logic divider can be used for RX to save power. Both dividers are capable of producing a tight relation between four quadrature output phases at low voltage and low power. Frequency tuning is achieved through digital control of the varactors which serve as an RF DAC. Combining a MIM capacitor array and two nMOS transistor arrays of the varactors for the RF DAC, a highly linear oscillator gain which is also insensitive to process shift is achieved. The finest varactor step size is 12 kHz at the 1.6-2.0 GHz output. With a sigma-delta dithering, high frequency resolution is obtained while having negligible phase noise degradation. The measured phase noise of -167 dBc/Hz at 20 MHz offset from 915 MHz carrier and frequency tuning range of 24.5% proves that this DCO system can be used in SAW-less quad-band transmitters for mobile phones.     

一种用于短距离无线通信并集成频率合成器的多模式多频带发射机

A reconfigurable multi-mode direct-conversion transmitter(TX) with integrated frequency synthesizer(FS) is presented. The TX as well as the FS is designed with a flexible architecture and frequency plan, which helps to support all the 433/868/915 MHz ISM band signals, with the reconfigurable bandwidth from 250 kHz to 2 MHz. In order to save power and chip area, only one 1.8 GHz VCO is adopted to cover the whole frequency range. All the operation modes can be regulated in real time by configuring the integrated register-bank through an SPI interface. Implemented in 180 nm CMOS, the FS achieves a frequency coverage of 320-460 MHz and 620- 920 MHz. The lowest phase noise can be -107 dBc/Hz at a 100 kHz offset and -126 dBc/Hz at a 1 MHz offset. The transmitter features a C10:2 dBm peak output power with a C9:5 dBm 1-dB-compression point and 250 kHz/500 kHz/1 MHz/2 MHz reconfigurable signal bandwidth.     

A 0.25-/spl mu/m CMOS quad-band GSM RF transceiver using an efficient LO frequency plan

This paper describes a single-chip CMOS quad-band (850/900/1800/1900 MHz) RF transceiver for GSM/GPRS applications. It is the most important design issue to maximize resource sharing and reuse in designing the multiband transceivers. In particular, reducing the number of voltage-controlled oscillators (VCOs) required for local oscillator (LO) frequency generation is very important because the VCO and phase-locked loop (PLL) circuits occupy a relatively large area. We propose a quad-band GSM transceiver architecture that employs a direct conversion receiver and an offset PLL transmitter, which requires only one VCO/PLL to generate LO signals by using an efficient LO frequency plan. In the receive path, four separate LNAs are used for each band, and two down-conversion mixers are used, one for the low bands (850/900 MHz) and the other for the high bands (1800/1900 MHz). A receiver baseband circuit is shared for all four bands because all of their channel spaces are the same. In the transmit path, most of the building blocks of the offset PLL, including a TX VCO and IF filters, are integrated. The quad-band GSM transceiver that was implemented in 0.25-/spl mu/m CMOS technology has a size of 3.3/spl times/3.2 mm/sup 2/, including its pad area. From the experimental results, we found that the receiver provides a maximum noise figure of 2.9 dB and a minimum IIP3 of -13.2dBm for the EGSM 900 band. The transmitter shows an rms phase error of 1.4/spl deg/ and meets the GSM spectral mask specification. The prototype chip consumes 56 and 58 mA at 2.8 V in the RX and TX modes, respectively.     

A Low-power and Low-complexity Baseband Processor for MIMO-OFDM WLAN Systems

This paper presents an energy-efficient design and the implementation results of a high speed two transmitter—two receiver multi-input multi-output orthogonal frequency division multiplexing (MIMO-OFDM) wireless LAN baseband processor. The proposed processor includes a bit-parallel processing physical layer convergence procedure (PLCP) processor which lowers system clock frequency. A cost-efficient MIMO spatial multiplexing (SM) symbol detector is also proposed in a physical medium dependent (PMD) processor. The proposed symbol detection algorithm is based on a sorted QR decomposition (SQRD) scheme followed by a maximum-likelihood (ML) test. The proposed algorithm shows enhanced performance compared to the conventional algorithms such as SQRD and ordered successive interference cancellation (OSIC) algorithms. The proposed baseband processor supports a maximum data rate of 130 Mbps at a 40 MHz operation frequency. The power consumptions of the PLCP processor are 27 mW and 93 mW for TX and RX modes, respectively, which are reduced by 70% compared with that of a common bit-serial architecture. The complexity of the symbol detector in the PMD processor is reduced by 18% compared with that of the conventional hardware architecture.     

A 4 Gb/s 3-bit Parallel Transmitter With the Crosstalk-Induced Jitter Compensation Using TX Data Timing Control

By using the data timing control at the transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 3-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 $mu{hbox {m}}$ CMOS process. The measurement shows that the proposed TX reduces the RX jitters by about 30 ps (more than 50% of the added jitter due to CIJ and ISI) at the data rates from 2.6 Gb/s to 4.0 Gb/s. The proposed scheme can be applied to more than three parallel microstrip lines.