Possible new mechanism of chip latent damage due to ESD

This paper introduces a possible new, to-date not recognized mechanism of microelectronic chip damage due to ESD as well as numerical simulation of some corresponding damage scenarios for an ESD protection device.The model presented herein recognizes the effects of thermo-mechanical coupling that can produce excessive mechanical stresses, elastic shock waves and mechanical damage in a chip during an ESD event. This mechanism can get activated at temperatures well below melting point and thus may be an early contributor to latent and “hard” ESD failures.     

Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-μm CMOS technology

NMOS-based power-rail ESD clamp circuits with gate-driven mechanism have been widely used to obtain the desired ESD protection capability. All of them are usually based on a similar circuit scheme with multiple-stage inverters to drive the main ESD clamp NMOS transistor with large device dimension. In this work, the designs with 3-stage inverter and 1-stage inverter controlling circuits have been studied to verify the optimal circuit schemes in the NMOS-based power-rail ESD clamp circuits. Besides, the circuit performances among the main ESD clamp NMOS transistors drawn in different layout styles cooperated with the controlling circuit of 3-stage inverters or 1-stage inverter are compared. Among the NMOS-based power-rail ESD clamp circuits, an abnormal latch-on event has been observed under the EFT test and fast power-on condition. The root cause of this latch-on failure mechanism has been clearly explained by the emission microscope with InGaAs FPA detector.     

Impact of ESD-induced soft drain junction damage on CMOS product lifetime

The impact of ESD-induced soft drain junction damage on product lifetime was investigated. Several thousand input-output (IO) pads of a 0.35 pm CMOS IC were stressed by ESD (electrostatic discharge) and subsequently subjected to bakes, ESD re-stress and high temperature operating life tests. While the ESD-induced soft drain junction damage appears to be stable versus temperature stress and ESD-re-stress, it results in early failures during accelerated operating life tests. These lifetest failures are caused by breakdown of the gate oxide which was left unbroken during the ESD stress that caused the ESD-induced soft drain junction damage. Thus, ESD-induced soft drain junction damage might cause a reliability risk (latent ESD failure). Consequently, it needs to be avoided by assuring a sufficient robustness of the IC against this ESD damage mechanism. A leakage current criterion of I VA is rather large to detect this kind of damage after ESD stress.     

Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-μm CMOS process

In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits.     

IGBT modules robustness during turn-off commutation

The behaviour in terms of robustness during turn-off of power IGBT modules is presented. The experimental characterisation is aimed to identify the main limits during turn-off in power IGBT modules in typical hard switching applications. In this paper an experimental characterization of high power IGBT modules at output currents beyond RBSOA, at high junction temperatures and under different driving conditions is presented. Several devices of different generations, current and voltage ratings have been considered. The experimental characterisation has been performed by means of a non-destructive experimental set-up where IGBT modules are switched in presence of a protection circuit that is able to prevent device failure at the occurrence of any possible instable behaviour. The experimental analysis confirms the very good robustness of high power IGBT modules which can withstand large current overstress well beyond the declared RBSOA limits even at temperatures larger than those one declared by manufacturers. A comparison between IGBT device generation is also presented.     

Electrostatic discharge in semiconductor devices: an overview

Electrostatic discharge (ESD) is an event that sends current through an integrated circuit (IC). This paper reviews the impact of ESD on the IC industry and details the four stages of an ESD event: (1) charge generation, (2) charge transfer, (3) device response, and (4) device failure. Topics reviewed are charge generation mechanisms, models for ESD charge transfer, electrical conduction mechanisms, and device damage mechanisms leading to circuit failure     

IGBT作为硬开关和软开关应用的模拟

建立了用ＰＳＰＩＣＥ软件包模拟ＩＧＢＴ特性的等效电路模型,并利用此模型模拟了ＩＧＢＴ的硬开关和软开关特性。模拟结果表明,ＩＧＢＴ作为硬开关的关断电流波形由器件本身决定;作为软开关的关断电流波形则由外电路决定,即由与器件相联接的缓冲电容Ｃｓ决定。得到的结论是,器件与电路的互相影响能够有效地用来折中器件的功率损耗与开关速度。     

一种新型低漏电ESD电源箝位电路

在到达纳米级工艺后,传统的静电放电防护(ESD)电源箝位电路的漏电对集成电路芯片的影响越来越严重。为降低漏电,设计了一种新型低漏电ESD电源箝位电路,该箝位电路通过2个最小尺寸的MOS管形成反馈来降低MOS电容两端的电压差。采用中芯国际40 nm CMOS工艺模型进行仿真,结果表明,在相同的条件下,该箝位电路的泄漏电流仅为32.59 nA,比传统箝位电路降低了2个数量级。在ESD脉冲下,该新型ESD箝位电路等效于传统电路,ESD器件有效开启。     

A double RESURF LDMOS with drain profile engineering for improvedESD robustness

This letter reports a novel 50 V lateral power MOSFET structure that is self-protecting with respect to electrostatic discharge (ESD) strikes. This device features a double RESURF technique in conjunction with a deep drain engineered profile that eliminates soft leakage degradation after snapback, thus demonstrating immunity to filamentation. Maximum second breakdown current (I_t2) of 16 mA/μm has been realized in a 100 ns transmission line pulse (TLP) measurement even with a higher holding voltage of 20 V. ESD protection level in excess of 5 kV with an equivalent human body model (HBM) has been shown to be feasible for this device without significant compromise in device size     

Reverse‐Conducting IGBT Using MEMS Technology on the Wafer Back Side

In this paper, we present a 600‐V reverse conducting insulated gate bipolar transistor (RC‐IGBT) for soft and hard switching applications, such as general purpose inverters. The newly developed RC‐IGBT uses the deep reactive‐ion etching trench technology without the thin wafer process technology. Therefore, a freewheeling diode (FWD) is monolithically integrated in an IGBT chip. The proposed RC‐IGBT operates as an IGBT in forward conducting mode and as an FWD in reverse conducting mode. Also, to avoid the destructive failure of the gate oxide under the surge current and abnormal conditions, a protective Zener diode is successfully integrated in the gate electrode without compromising the operation performance of the IGBT.     

Statistical analysis of characteristic of ageing precursor of IGBT based on synthetic effect of multi-physical fields

The IGBT power modules are widely used in photovoltaic power generation, high-voltage direct current transmission and other fields. Due to the need for high reliability in the application fields, the industry is very concerned about the reliability of IGBT power modules. Based on the two different working conditions of the three-level NPC photovoltaic inverter, this paper has monitored the health status of bonding wires of the IGBT modules inside the inverter. In addition, for the experimental results of monitoring, theoretical analysis and experimental demonstration from the perspective of multi-physics (temperature field, electromagnetic field, etc.) are innovatively introduced, which provides a new perspective for the research of power module reliability.     

Instable mechanisms during unclamped operation of high power IGBT modules

The behaviour in terms of robustness during unclamped operations of power IGBT modules is presented. The experimental characterization is aimed to identify the main instable phenomena during unclamped turn-off in power IGBT modules. Several devices of different generations, current and voltage ratings have been analyzed. Thanks to a non-destructive experimental set-up, it is possible to observe instable phenomena without causing the damage of the device under test. In this paper, it is shown that the destructive conditions during unclamped operations are preceded by precursors on the gate side which indicate instable phenomena taking place inside the device. The dependence of the destructive phenomenon on the driver conditions are widely and exhaustively analyzed.     

Thermo-mechanical simulation of a multichip press-packed IGBT

The reliability of press-packed integrated gate bipolar transistors (IGBT) depends on satisfactory contact conditions applied at assembly stage and mantained throughout the service life. The objective of this work is the simulation of the thermo-structural behavior of a multichip IGBT during initial assembly and subsequent uniform thermal cycling using the finite element method. A detailed axisymmetric FE model of the 3D-device is developed to assess multi-zone contact conditions. Elastic-plastic material behavior and Coulombian friction on contact surfaces are prescribed. The role of dimensional tolerances on contact conditions is discussed. The thermal cycling associated to accelerated testing is then introduced to determine the contact pressure evolution as well as local stick/slip conditions. The device sensitivity to potential damage initiation due to thermo-mechanical fatigue and/or fretting is addressed.     

Multilevel inverter by cascading industrial VSI

In this paper, the modularity concept applied to medium-voltage adjustable speed drives is addressed. First, the single-phase cascaded voltage-source inverter that uses series connection of insulated gate bipolar transistor (IGBT) H-bridge modules with isolated DC buses is presented. Next, a novel three-phase cascaded voltage-source inverter that uses three IGBT triphase inverter modules along with an output transformer to obtain a 3-p.u. multilevel output voltage is introduced. The system yields in high-quality multistep voltage with up to four levels and low dv/dt, balanced operation of the inverter modules, each supplying a third of the motor rated kVA. The concept of using cascaded inverters is further extended to a new modular motor-modular inverter system where the motor winding connections are reconnected into several three-phase groups, either six-lead or 12-lead connection according to the voltage level, each powered by a standard triphase IGBT inverter module. Thus, a high fault tolerance is being achieved and the output transformer requirement is eliminated. A staggered space-vector modulation technique applicable to three-phase cascaded voltage-source inverter topologies is also demonstrated. Both computer simulations and experimental tests demonstrate the feasibility of the systems.     

Undeland缓冲电路在IGBT逆变桥中的应用

将Undeland缓冲电路用于IGBT逆变桥中,通过合理的归并元器件,提出了一种简单、实用的多桥臂逆变电路缓冲拓扑结构。并通过一个400 Hz逆变电路的仿真和实验波形得到验证。     

高压LDMOS器件ESD初始失效问题及其优化方向研究

研究了LDMOS在ESD放电过程中的机理及二次触发的现象,通过对LDMOS器件关键尺寸的优化设计与结构的改进,结合器件计算机辅助设计技术(TCAD)仿真、传输线脉冲(TLP)测试以及失效分析(FA)等手段,改善了其初始失效问题。同时大幅提升了LDMOS的ESD泄放能力,并进一步总结了LDMOS器件的ESD性能的优化方向。     

数字锁相控制的IGBT感应加热电源

以20 kHz/10 kW中频电源为设计对象,设计了采用三相不控整流和串联谐振逆变器的IGBT淬火感应电源.给出了其功率主电路器件的具体参数并通过Simulink仿真为实验装置提供了依据;根据IGBT的驱动要求,选择驱动器SKHI 22A详细研究了IGBT的驱动电路及其外围电路的设计;锁相控制电路由CD4046和DSP...     

柔性线路板串扰PSpice仿真分析及应用

通过场仿真器获得柔性线路板三导线传输线系统电感电容矩阵,进而得到传输线PSpice模型,并对实际的静电放电干扰进行模拟,从改变实际产品布线结构的角度减小相邻线路脉冲干扰对器件自身的串扰噪声损伤,有利于产品前期的设计改进。     

IGBT器件可靠性评估中建模及参数提取的研究

IGBT器件的失效是与其动态特性相关的复杂过程,涉及到电热机械等多方面因素,如何描述这一过程是掌握器件可靠性的基础。本文从IGBT的导电机理出发,提出采用二极管势垒电容表征其内部寄生电容的方法,建立了IGBT的电路模型,描述其动态特性,并以子电路形式集成到PSPICE软件中。最后进行了模型验证和敏感度分析,结果证实该模型在描述IGBT动态特性方面的效果是可以接受的。     

Envelop tracking based embedded current measurement for monitoring of IGBT and power converter system

Health monitoring of the power conversion system is very important. Therefore, we developed a new method for measuring IGBT currents and reproducing average load current to monitor IGBTs. This method was successfully tested on an experimental setup which showed that the tiny PCB sensors can be integrated into intelligent power modules. We proposed an inexpensive analogue circuit which is suitable for capturing current information from a tiny PCB Rogowski coil. The sensors and corresponding circuit can be embedded into an Intelligent Power Module. The method was named “Envelop tracking” as it simultaneously measures the currents of the high and low side switches of a power converter and reproduces the upper and lower edges of the load current which can be averaged by further digital processing.