ANALOG CIRCUIT IMPLEMENTATION OF NEURAL NETWORK WITH HIGH PRECISION WEIGHTS

A current-mode MOS neuron circuit with 4-bit programmable weights is presented by using CMOS technology. The weights of the neurcn have high resolution and also can easily be digitally stored. The resolution can be extended into high levels such as 8-bit, etc. by the design methodology presented in this paper. The operational principle of the neuron is discussed. Circuit simulation has been made by use of SPICE II. The results give a good agreement for the design requirements.     

Analog phase measuring circuit for digital CMOS ICs

A circuit measuring the phase of incoming asynchronous signals relative to the system clock in digital signal processing is described. The system clock can be in the range from 10 to 20 MHz, as is typical for video signal processing applications. As a reference in the asynchronous signal the positive or negative slope is taken. Its phase is measured with a resolution of 1/32 of a system clock cycle (approximately 1.5 to 3 ns). Pure digital CMOS technology without precision components is used, to enable combined integration on processor chips. Timing precision (jitter) is better than 200 ps without any adjustments. One external capacitor is needed     

A circuit implementation of a single-bit CMOS adder

In this article, a circuit implementation of a single-bit CMOS adder with enhanced performance is presented. The adder circuit consists of separate circuits operating in-parallel for obtaining the output sum and carry signals. The carry circuit signal is not used to form the sum signal. The sum signal circuit is a sequential connection of two XOR cells. The circuit operability is confirmed by the results of circuit simulation using Cadence Design Systems’ software.     

基于CPLD的高帧频CMOS相机驱动电路设计

依据Micron公司MI-MV13型高帧频互补金属氧化物半导体(CMOS)图像传感器驱动控制时序关系,设计了高帧频相机驱动控制时序.选用Actel公司复杂的可编程逻辑器件及其开发系统,并利用硬件描述语言实现了驱动时序及控制时序.实验表明,设计的控制驱动时序完全能满足图像传感器的要求.     

New CMOS circuit implementation of a one-bit full-adder cell

A new mirror CMOS circuit implementation of a one-bit full-adder cell is proposed. Using CMOS technology provides zero static power consumption and the freedom from fractional voltage levels at the internal nodes (no voltage recovery is needed). The solution proposed is shown to be superior in carry speed to any alternative CMOS implementation reported so far, and should therefore be suitable for building high-speed multibit adders.     

Analog CMOS implementation of a CNN-based locomotion controller with floating-gate devices

This paper proposes an analog CMOS circuit that implements a central pattern generator (CPG) for locomotion control in a quadruped walking robot. Our circuit is based on an affine transformation of a reaction-diffusion cellular neural network (CNN), and uses differential pairs with multiple-input floating-gate (MIFG) MOS transistors to implement both the nonlinearity and summation of CNN cells. As a result, the circuit operates in voltage mode, and thus it is expected to reduce power consumption. Due to good matching accuracy of devices, the circuit generates stable rhythmic patterns for robot locomotion control. From experimental results on fabricated chip using a standard CMOS 1.5-/spl mu/m process, we show that the chip yields the desired results; i.e., stable rhythmic pattern generation and low power consumption.     

Analog CMOS circuit design and characterization for optical coherence tomography signal processing

We have developed a custom analog CMOS circuit to perform the signal processing for an optical coherence tomography imaging system. The circuit is realized in a 1.5 /spl mu/m low-noise analog CMOS technology. The circuitry extracts the Doppler frequency from the signal and electrically mixes this with the original signal to provide a filtered A-scan. The circuitry was used to produce a two-dimensional image of an onion.     

一种高精度CMOS微弱电流读出电路

本文介绍了一种高精度CMOS微弱电流读出电路。该电路能够将十分微弱的电流信号精确地转化为频率信号以用于电流的测量,并将结果转化为10位数字信号输出。本设计提出了一种快速的稳定增强型恒电位仪,该恒电位仪能为安培型生化传感器提供恒定的偏置电压。电路中还采用了源极电压转移技术,在室温条件下,该技术能使MOS管的漏电流降低到反向偏置二极管的漏电流水平,大大提高了电流检测的精度。该芯片采用了新加坡特许半导体公司0.35μm标准CMOS工艺,电源电压3.3V。该读出电路具有超过100dB的大动态范围,能够精确地检测出从1pA到300nA的电流,且全量程范围内非线性误差不超过0.3%。     

Analog VLSI implementation of spatio-temporal frequency tuned visual motion algorithms

The computation of local visual motion can be accomplished very efficiently in the focal plane with custom very large-scale integration (VLSI) hardware. Algorithms based on measurement of the spatial and temporal frequency content of the visual motion signal, since they incorporate no thresholding operation, allow highly sensitive responses to low contrast and low-speed visual motion stimuli. We describe analog VLSI implementations of the three most prominent spatio-temporal frequency-based visual motion algorithms, present characterizations of their performance, and compare the advantages of each on an equal basis. This comparison highlights important issues in the design of analog VLSI sensors, including the effects of circuit design on power consumption, the tradeoffs of subthreshold versus above-threshold MOSFET biasing, and methods of layout for focal plane vision processing arrays. The presented sensors are capable of distinguishing the direction of motion of visual stimuli to less than 5% contrast, while consuming as little as 1 /spl mu/W of electrical power. These visual motion sensors are useful in embedded applications where minimum power consumption, size, and weight are crucial.     

抗多源激光高重频干扰新方案及电路实现

多源激光高重频干扰和抗多源激光高重频干扰是激光对抗的重要形式,多源高重频干扰对抗中高重频信号识别和处理的难度更高.为此,提出了一种抗多源激光高重频干扰的新方案,该方案的核心是按制导信号周期进行延时后的信号与实时信号进行与操作.提出了多芯片使用同一振荡电路解决模拟实验中零漂问题的技术途径.得出了许多电路实验验证结果:制导信号和高重频干扰信号的复合模拟结果,多芯片使用同一振荡电路与不使用同一振荡电路的渡门内信号的模拟结果,电路输出信号与输入制导信号的对比结果.结果表明:高重频干扰信号被高概率地滤除,电路输出信号为制导信号,抗多源激光高重频干扰新方案可行.该方案为激光对抗提供了一种新方法.     

基于CMOS的电子传感接收电路的设计与实现

当前电子传感接收电路具有能耗高、性能参数不符合要求的弊端。为此,设计一种新的基于CMOS的电子传感接收电路,并介绍了电子传感接收电路设计方案。依据设计方案,选用源级负反馈电感匹配结构对低噪声放大器的基本电路结构进行设计;为达到性能指标和降低功耗,混频器电路结构选用无源双平衡混频器结构;为了降低整个电子传感接收电路的能耗,令无源双平衡混频器的开关MOS管在无电流偏置的情况下运行。给出了复数滤波器设计的基本思想,通过反馈系统对编程增益放大器的增益进行管理,实现可编程放大器的设计。实验结果表明,所设计电路性能符合设计要求。     

A high precision CMOS weak current readout circuit

rents from 1 pA to 300 nA can be detected with a maximum nonlinearity of 0.3% over the full scale.     

A high performances CMOS CCII and high frequency applications

In this paper, we propose an improved translinear based CCII configuration. Heuristic algorithm is used for optimal sizing regarding static and dynamic performances. PSPICE simulations for AMS 0.35 μm CMOS technology show that the current and voltage bandwidths are respectively 2.6 GHz and 3.9 GHz, and the parasitic resistance at port X (R _X ) has a value of 18 Ω for a control current of 100 μA. The improved configuration is used as a building block into high frequency design applications: a current controlled oscillator and a tunable fully integrable band pass filter. The oscillator frequency can be tuned in the range of [290–475 MHz] by a simple variation of a DC current. The central frequency of the band pass filter can be varied in the range of [1.22–1.56 GHz] and the quality factor vary in the range [8–306] with a simple variation of a DC current.     

电机控制器中的CMOS电路节能设计与实现

为了提高电机控制器的输出功率增益,增强电机的节能性和控制稳定性,提出基于CMOS数字集成电路进行电机控制器的节能电路优化设计方案。电机控制器的电路设计主要由交流放大电路、滤波电路、电压温漂抑制电路和微调电路等模块组成,采用CMOS电压控制放大器作为核心器件,提高电机控制器输出基准的稳定性。通过电路模块化分析和集成化设计,实现电机控制器优化设计。电路测试结果表明,设计的电机控制器具有较高的输出增益,电机输出效率得到提高。     

一种超宽带CMOS除二电路及其优化方法

本文提出了一种新型的基于轮换触发的除二电路及其基于大信号分析的优化方法。通过减小跟随相输出节点的RC常数,增大锁存相输出节点的RC常数,减小内部信号摆幅和补偿锁存相输出节点漏电流的损失等电路技术,大大拓宽了其工作频带。本论文在SMIC 0.13μm RF CMOS工艺条件下设计了一款原型电路,其后仿工作频率可以达到320MHz到29.6GHz。此外,这款除二电路还应用于两款整数分频锁相环芯片中,分别对频率为4224MHz和10GHz的信号进行分频。测试结果表明,这款除二电路可以对其进行正确分频,而且整体锁相环的带内相噪分别为-94dBC/Hz@10kHz和-84dBc/Hz@10kHz.     

Design and optimization of an ultra-wide frequency range CMOS divide-by-two circuit

A novel toggled flip-flop(TFF) divide-by-two circuit(DTC) and its optimization method based on a large-signal analysis approach are proposed.By reducing the output RC constant in tracking mode and making it large in latching mode,compressing the internal signal swing as well as compensating the current leaked in the latching mode, the operating frequency range is greatly expanded.Implemented in a SMIC 0.13μm RF CMOS process with a 1.2 V power supply,it can work under an ultra-wide frequency band ranging ...     

CMOS电路中外部能耗控制模块的设计与实现

传统的大规模集成电路的功耗控制方法存在运算量高、精确度有限的问题。因此,基于双阈值低功耗技术设计并实现CMOS电路中外部能耗控制模块,采用双阈值电压技术通过较低阈值的晶体管设计CMOS能耗控制模块。通过高阈值电压的NMOS管控制低阈值模块,降低电路的泄露电流,使用低阈值模块中的NMOS管对CMOS门单元电路进行管理,提高门单元电路的运行效率,降低总体CMOS电路的功耗。采用双阈值技术设计CMOS电路的单边沿脉冲触发器,对触发器的时钟响应电路进行优化,确保时钟翻转通过数字信号进行管理,极大降低时钟翻转频率,减小电路动态功耗。实验结果表明,所设计模块具有较高的控制效率,较低的延迟和功耗,其控制下的CMOS电路节能效果显著。     

Gain-compensated sample-and-hold circuit for high frequency application

A novel and fast and accurate sample-and-hold circuit is presented which can be designed using conventional single stage amplifiers. The offset contribution to the output voltage is intrinsically compensated and the clock-feedthrough error can be reduced by slightly changing the clock phase scheme.<>     

一种高带宽NP 型CMOS APD 的研究

提出了一种高带宽的硅基CMOS雪崩光电二极管(APD)器件。该器件在N阱/P衬底基本结构的基础上,增加一个N型深掩埋层,并在该掩埋层单独加上电压,以减小载流子的输运时间。通过理论分析确定了器件的结构参数,通过器件性能的仿真分析对相关参数进行了优化设计。仿真结果表明:采用标准0.18 m CMOS工艺,所设计的APD器件的窗口尺寸大小为20 m20 m,在反向偏压为16.3 V时,器件的雪崩增益为20,响应度为0.47 A/W,3 dB带宽为8.6 GHz。