超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法     

PMOSFET的NBTI效应

随着工艺的发展,器件尺寸的不断缩小,PMOSFET受负温度不稳定性(NBTI)效应影响而失效的现象愈来愈严重,NBTI效应的影响成为器件可靠性的一个焦点问题.本文综述了NBTI效应的产生机理、影响因素、减缓方法及其相关的一些前沿问题.     

超深亚微米PMOSFET器件的NBTI效应

研究了超深亚微米PMOS器件中的NBTI(负偏置温度不稳定性)效应,通过实验得到了NBTI效应对PMOSFET器件阈值电压漂移的影响,并得到了在NBTI效应下求解器件阈值电压漂移的经验公式.分析了影响NBTI效应的主要因素:器件栅长、硼穿通效应和栅氧氮化以及其对器件寿命退化的作用.给出了如何从工艺上抑制NBTI效应的方法.     

沟道宽度对65nm金属氧化物半导体器件负偏压温度不稳定性的影响研究

随着MOS器件尺寸缩小,可靠性效应成为限制器件寿命的突出问题.PMOS晶体管的负偏压温度不稳定性（NBTI）是其中关键问题之一.NBTI效应与器件几何机构密切相关.本文对不同宽长比的65nm工艺PMOSFET晶体管开展了NBTI试验研究.获得了NBTI效应引起的参数退化与器件结构的依赖关系,试验结果表明65nm PMOSFET的NBTI损伤随沟道宽度减小而增大.通过缺陷电荷分析和仿真的方法,从NBTI缺陷产生来源和位置的角度,揭示了产生该结果的原因.指出浅槽隔离（STI）区域的电场和缺陷电荷是导致该现象的主要原因.研究结果为器件可靠性设计提供了参考.     

PMOSFET动态NBTI效应的研究

负偏压温度不稳定性效应(NBTI)已经成为影响CMOS集成电路可靠性的一个关键因素,而动态应力条件下的NBTI效应对器件和电路的影响越来越受到关注。对PMOSFET的动态NBTI效应进行了系统介绍,讨论了动态应力条件下NBTI(DNBTI)效应和静态应力下NBTI(SNBTI)退化机理,综述了DNBTI效应的动态恢复机制以及影响因素,最后介绍了NBTI效应对电路的影响。随着器件尺寸的日益缩小,如何提高电路的可靠性变得日益重要,进一步研究NBTI效应对电路的影响从而进行NBTI电路级可靠性设计已成为集成电路设计关注的焦点。     

超深亚微米P^＋栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P^ 栅PMOSFET中的NBTI效应，首先通过实验分析了NBTI应力后器件特性及典型参数的退化，基于这些实验结果提出了一种可能的NBTI效应发生机制：即由水分子参与的Si—SiO2界面处的电化学反应．最后从工艺的角度给出了减小和抑制NBTI效应的方法．     

纳米PMOSFET负偏压温度不稳定性测试方法

P型金属氧化物半导体场效应晶体管(PMOSFET)的负偏压温度不稳定性(NBTI)是制约纳米MOS器件在长寿命电子系统中应用的关键问题之一。为了准确地表征NBTI效应对器件参数的影响,分析了现有测试方法的特点,在此基础上改进了测试试验方法。利用该方法对90nm体硅工艺器件的NBTI效应进行了测试和分析,结果表明该方法能够很好地避免间断应力方法造成的参数快速恢复,获得更加准确的试验数据。     

NBTI的研究进展和改善途径

本文首先介绍了发生于PMOSFET器件上的NBTI（负偏压温度不稳定性）的基本理论,介绍了NBTI的两种衰退机理（反应-扩散模型和电荷俘获-脱离模型）,指出它们各自的适用范围,并针对新的NBTI测试方法的采用,探讨了对可靠性性能估计的影响。最后总结了遏制NBTI效应的研究成果。     

超深亚微米P+栅PMOSFET中NBTI效应及其机理研究

本文深入研究了P⁺栅PMOSFET中的NBTI效应,首先通过实验分析了NBTI应力后器件特性及典型参数的退化,基于这些实验结果提出了一种可能的NBTI效应发生机制:即由水分子参与的Si-SiO₂界面处的电化学反应.最后从工艺的角度给出了减小和抑制NBTI效应的方法.     

NBTI效应的退化表征

对超深亚微米PMOSFET器件NBTI效应的失效机理和退化表征进行了讨论.反应-扩散模型是最为广泛接受的NBTI退化机理模型,它有效地解释了阈值电压漂移随时间逐渐饱和以及应力去除后NBTI效应部分恢复的退火现象.用阈值电压漂移量表征了NBTI效应的退化,深入讨论了影响NBTI效应的主要因素:应力作用时间、栅氧电场和温度应力,总结了阈值电压漂移与这些因素的关系,给出了一个经验-逻辑推理公式,对公式中的参数提取后可以得到NBTI寿命值,从而实现NBTI效应的可靠性评价.     

On the Formation of Positive Charges in Ultrathin Silicon-Oxynitride p-MOSFETs Subjected to Negative Bias Temperature Stress

p-MOSFET negative bias temperature instability (NBTI) has become the most important reliability issue for the CMOS industry. This letter investigates the formation of oxide positive charges (PCs) and its effects on the NBTI. Evidence shows that PC dominates NBTI at stress temperature lower than 373 K, whereas interface-state generation has an obvious contribution above 373 K. Two kinds of PC are distinguished as follows: The trapped holes are the main origin of NBTI at lower temperatures, and the generated PC plays a role at higher temperatures. The physical mechanisms of the two kinds of PC are also discussed in this letter.     

Evidence for bulk trap generation during NBTI phenomenon in pMOSFETs with ultrathin SiON gate dielectrics

Negative bias temperature instability (NBTI) of pMOSFETs with direct-tunneling SiON gate dielectrics was studied in detail. By investigating the effects of applying positive gate bias on pMOSFETs after exposure to NBT stress, the generation of bulk charge traps in the gate dielectrics during NBTI was clearly demonstrated. In particular, it was found that a positive charge generated by negative bias temperature stress (NBT stress) can be neutralized and that the neutralized site can return to the positive state. We consider that the bulk trap is due to hydrogen atoms released from the interface between the SiON gate dielectric and the Si substrate (and this is what has conventionally been considered a positive fixed charge). Moreover, the bulk trap generation was shown to give rise to stress-induced leakage current.     

Mechanism of nitrogen-enhanced negative bias temperature instability in pMOSFET

From the detailed analysis of the dependence of threshold voltage shift and positive fixed charge/interface state generation on the stress time/temperature of negative bias temperature instability (NBTI) for various nitrogen concentrations at the oxide/Si interface, the mechanism of nitrogen-enhanced NBTI effect has been studied experimentally. The experimental results can be understood in terms of the reaction energies of the hydrogen trapping reactions at the interface, which are obtained from first-principles calculations. The calculations show that the nitrogen's lone-pair electrons can trap dissociated hydrogen species more easily than oxygen. From the experimental and theoretical studies, one can conclude that the roles of nitrogen in the NBTI are two folds, i.e., it provides more reaction sites, and it can also enhance the NBTI reaction by reducing the reaction energy.     

Positive bias temperature instability in MOSFETs

The positive bias temperature instability (PBTI) of submicron MOSFETs has been investigated. It is found that the PBTI can be as large as the well-known negative bias temperature instability (NBTI). While the NBTI includes both Interface state generation and positive charge formation in the gate oxide, the PBTI only exists in the form of donor-like interface state generation. These donor-like interface states are localized symmetrically near the source and drain junctions and are negligible in the middle of the channel. Their dependence on the stressing electrical field strength and temperature is investigated and an activation energy of 1.23 eV is extracted. The PBTI creation follows the first order kinetics and the final saturation level is fixed by the number of defects available in the device. The experimental results show that the water- and boron-related species are two necessary reactants of the electrochemical reaction leading to the PBTI. Some speculation on the PBTI formation process is included     

A New NBTI Model Based on Hole Trapping and Structural Relaxation in MOS Dielectrics

Negative bias temperature instability (NBTI) is one of the major reliability concerns for analog and digital MOS devices. NBTI understanding and modeling is receiving a growing interest for failure prediction, depending on the temperature and duty cycle of dynamic-stress conditions. In this framework, we present a new NBTI model based on hole trapping and thermally activated relaxation. The model unifies previous concepts of hole tunneling/trapping and structural relaxation initiated by hole trapping. Simulation results can account for the time and temperature dependence of NBTI stress, NBTI recovery, and the dependence on thickness and nitridation technology of the gate dielectric. The numerical model may be used for physics-based reliability predictions of NBTI effects as a function of time, temperature, and stress regime.      

数字电路中NBTI效应仿真及建模方法的研究

负偏压温度不稳定性(NBTI)效应已成为影响数字电路设计的重要可靠性问题之一。首先讨论了PMOS晶体管中NBTI效应对数字电路的影响,提出针对不同工艺PMOS管中NBTI效应建模的流程,设计了一种基于SPICE模型的NBTI仿真模型。该模型能够通过Cadence软件调用,并在实际的数字电路设计中进行动态仿真,预测NBTI效应对电路性能的影响。基于该建模流程,在Cadence软件中对基于40 nm工艺的一级两输入与非门和四十级反相器组成的环形振荡器进行仿真。仿真结果表明,该模型能够对不同工艺下PMOS管中的NBTI效应进行准确、有效地仿真,为数字电路的可靠性设计提供保障。     

New NBTI models for degradation and relaxation kinetics valid over extended temperature and stress/recovery ranges

In this paper we present NBTI stress and recovery effects measured on PFET devices issued from various FDSOI technologies. NBTI degradation and recovery subsequent to DC stress are measured at the μs time scale. After in-depth analysis of temperature and stress/recovery bias effects, we propose new NBTI models for degradation and recovery kinetics including temperature, Vg_stress and Vg_recovery dependencies. These models are finally validated on different technologies and various experimental conditions.     

Reliability of Strained-Si Devices With Post-Oxide-Deposition Strain Introduction

To assess the impact of strain on negative bias temperature instability (NBTI), systematic studies were performed on devices with polycrystalline-Si/SiON as well as deposited metal gate/high- $kappa$ and FUSI/high-$kappa$ gate stacks. The effects of compressive stress, which acts as performance booster for PMOS devices, were studied, with strain introduced by stressor layers as well as SiGe source/drain techniques. Care was taken to account for side effects of processing steps used to introduce the strain, such as changes on threshold voltage or capacitance equivalent thicknesses, in order to obtain a fair evaluation of the intrinsic effect of strain on NBTI. NBTI measurements were complemented by charge pumping and noise measurements to obtain a comprehensive understanding of defects present and of their generation under stress. In addition, nanobeam diffraction strain measurements, as well as curvature mass simulations, were performed in order to investigate the impact of strain on carrier mobility in the vertical direction. Our studies showed consistently that there is no significant degradation of intrinsic NBTI behavior due to process-induced strain.