一种1.5 V 8位100 MS/s电流舵D/A转换器

基于新型的低压与温度成正比(PTAT)基准源和PMOS衬底驱动低压运算放大器技术,采用分段温度计译码结构设计了一种1.5V8位100MS/s电流舵D/A转换器,工艺为TSMC0.25μm2P5MCMOS。当采样频率为100MHz,输出频率为20MHz时,SFDR为69.5dB,D/A转换器的微分非线性误差(DNL)和积分非线性误差(INL)的典型值分别为0.32LSB和0.52LSB。整个D/A转换器的版图面积为0.75mm×0.85mm,非常适合SOC的嵌入式应用。     

一种16位600 MS/s电流舵D/A转换器的设计

基于0.18 μm CMOS工艺,设计了一种16位600 MS/s电流舵D/A转换器。该D/A转换器为1.8 V/3.3 V双电源供电,采用并行输入、差分电流输出的四分段(5+4+3+4)电流舵结构。采用灵敏放大器型锁存器可以精确锁存数据,避免出现误码;由恒定负载产生电路和互补交叉点调整电路组成的同步与开关驱动电路,降低了负载效应引起的谐波失真,同时减小了输出毛刺;低失真电流开关消除了差分开关对共源节点处寄生电容对D/A转换器动态性能的影响。Spectre仿真验证结果表明,当采样频率为625 MHz,输入信号频率为240 MHz时,该D/A转换器的SFDR为78.5 dBc。     

8通道14位60MHz电流舵型D/A转换器

以电流舵型D/A转换器为核心,设计了一个8通道14位60MHz D/A转换器。采用三段电流源(5+4+5)结构的核心D/A转换器单元,有效地保证了转换器的精度和速度;利用电荷泵锁相环进行时钟倍频和多组时钟信号的相位同步,确保电路动态性能;通过输入级引入失调来获得具有迟滞特性的低压差分信号(LVDS)接收器,实现了840 Mb/s高频数据接口功能。电路采用CMOS工艺,在60MHz时钟频率,2MHz模拟输出频率下,功耗小于1 W,无杂散动态范围大于72dB。     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

一种1.8V 10位120MS/s CMOS电流舵D/A转换器IP核

采用低摆幅低交叉点的高速CMOS电流开关驱动器结构和中心对称Q2随机游动对策拓扑方式的pMOS电流源阵列版图布局方式,基于TSMC 0.18靘 CMOS工艺实现了一种1.8V 10位120MS/s分段温度计译码电流舵CMOS电流舵D/A转换器IP核.当电源电压为1.8V时,D/A转换器的微分非线性误差和积分非线性误差分别为0.25LSB和0.45LSB,当采样频率为120MHz,输出频率为24.225MHz时的SFDR为64.9dB.10位D/A转换器的有效版图面积为0.43mm×0.52mm,符合SOC的嵌入式设计要求.     

采用熔丝修调技术的高精度电流舵D/A转换器

高精度D/A转换器的实际精度往往低于理论上的精度。针对这个长期困扰的难题,在设计16位D/A转换器的过程中,提出了一种熔丝修调技术,即通过修调电流源输出端的电流,有效地减小电流源失配和有限输出阻抗对D/A转换器的DNL和INL的影响,大幅度提高D/A转换器的精度。基于0.18 μm CMOS 工艺的测试结果表明:在采用熔丝修调技术前,该电路的DNL和INL分别为－0.72~9.07 LSB和－5.55~18.1 LSB;在采用熔丝修调技术后,该电路的DNL和INL分别为－3.95~0.70 LSB和1.94~8.06 LSB。当输入信号频率为102 MHz、采样频率为500 MHz时,SFDR达到82.16 dBc,完全满足D/A转换器高精度的要求。     

Wuxi Branch of Southeast University, Wuxi Jiangsu 214028, China; 2.The 58th Institute of China Electronic Technology Company, Wuxi Jiangsu 214035, China

在研究高速D/A转换器的基础上,设计了一种5 V 10 bit高速分段式温度计码D/A转换器.设计的5-1-4温度计译码电路以及对版图布局的优化,使得DAC的DNL和INL最小,该电路的核心由三段式温度计编码控制的47个电流源构成.基于上华0.5μm工艺,采用HSPICE仿真工具对其进行仿真,得到在200 MHz的采样频率下对50 Ω负载满量程输出为45mA,非线性误差为DNL＜0.5LSB,INL＜0.75LSB.     

直接数字频率合成信号发生器的设计

简要介绍了基于现场可编程门阵列(FPGA)及直接频率合成信号发生器(DDS)技术的信号发生器设计和实现.该设计采用CycloneⅡ系列器件EP2C8Q208C8实现DDS波形产生电路、D/A转换器控制及与ARM接口等功能,用先进精简指令单片机(ARM) STM32F103进行频率控制字、相位控制字,频率输出显示等控制.由于FPGA的晶振是50 MHz,经过增强型锁相环(PLL)后采样频率可达到250 MHz,通过14位400MSPS的高速数模转换器(DAC)和7阶椭圆低通滤波器,最终输出的正弦波最大频率可达到70 MHz.     

基于模拟余差的7位200MS/s分级折叠式A/D转换器

提出一种基于模拟余差的分级折叠式A/D转换器,对其原理和电路结构进行了分析,阐述了提高A/D转换器性能的关键问题.测试结果表明,设计的A/D转换器转换速率为200 MS/s;在输入信号为6.0 MHz时,信噪谐波比(SINAD)为45.1 dB,有效位数(ENOB)为7.2位.给出了A/D转换器电路的具体结构,以及测试波形和动态性能参数测试结果.     

0.18 μm 1.8 V 10 bit 100 MS/s CMOS电流舵D/A IP设计与验证

基于GSMC 0.18μm CMOS工艺,采用曲率补偿带隙参考电压源和中心对称Q2随机游动对策拓扑方式的NMOS电流源阵列版图布局,实现了一种10 bit 100 MS/s分段温度计译码CMOS电流舵D/A转换器.当电源电压为1.8 V时,D/A转换器的功耗为10 mW,微分非线性误差和积分非线性误差分别为1 LSB和0.5 LSB.在取样速率为100 MS/s,输出频率为5 MHz条件下,SFDR为70 dB,10 bit D/A转换器的有效版图面积为0.2 mm2,符合SOC的嵌入式设计要求.     

Performance improvement in tensile-strained In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As metamorphic HEMT

This paper proposes a In/sub 0.5/Al/sub 0.5/As/In/sub x/Ga/sub 1-x/As/In/sub 0.5/Al/sub 0.5/As (x=0.3-0.5-0.3) metamorphic high-electron mobility transistor with tensile-strained channel. The tensile-strained channel structure exhibits significant improvements in dc and RF characteristics, including extrinsic transconductance, current driving capability, thermal stability, unity-gain cutoff frequency, maximum oscillation frequency, output power, power gain, and power added efficiency.     

Morphological and electrical characterization of SixCryCzBv thin films

Si_xCr_yC_zB_v thin films with several compositions have been studied for integration of high precision resistors in 0.8 μm BICMOS technology. These resistors, integrated in the back-end of line, have the advantage to provide high level of integration and attractive electrical behavior in temperature, for analog devices. The film morphology and the structure have been investigated through transmission electron microscopy analysis and have been then related to the electrical properties on the base of the percolation theory. According to this theory, and in agreement with experimental results, negative thermal coefficient of resistance (TCR) has been obtained for samples with low Cr content, corresponding to a crystalline volume fraction below the percolation threshold.Samples with higher Cr content exhibit, instead, a variation of the TCR as a function of film thickness: negative TCR values are obtained for thickness lower than 5 nm, corresponding to a crystalline volume fraction below the percolation threshold; positive TCR are obtained for larger thickness, indicating the establishment of a continuous conductive path between the Cr rich grains. This property seems to be determinant in order to assure the possibility to obtain thin film resistors almost independent on the temperature.     

Comparison between Pt/TiO2/Pt and Pt/TaOX/TaOY/Pt based bipolar resistive switching devices

Nonvolatile memories have emerged in recent years and have become a leading candidate towards replacing dynamic and static random-access memory devices. In this article, the performances of TiO₂ and TaO₂ nonvolatile memristive devices were compared and the factors that make TaO₂ memristive devices better than TiO₂ memristive devices were studied. TaO₂ memristive devices have shown better endurance performances (10⁸ times more switching cycles) and faster switching speed (5 times) than TiO₂ memristive devices. Electroforming of TaO₂ memristive devices requires~4.5 times less energy than TiO₂ memristive devices of a similar size. The retention period of TaO₂ memristive devices is expected to exceed 10 years with sufficient experimental evidence. In addition to comparing device performances, this article also explains the differences in physical device structure, switching mechanism, and resistance switching performances of TiO₂ and TaO₂ memristive devices. This article summarizes the reasons that give TaO₂ memristive devices the advantage over TiO₂ memristive devices, in terms of electroformation, switching speed, and endurance.     

The C-V-f and G/ω-V-f characteristics of Al/SiO2/p-Si (MIS) structures

The frequency dependence of capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of the Al/SiO₂/p-Si metal-insulator-semiconductor (MIS) structures has been investigated taking into account the effect of the series resistance (R_s) and interface states (N_ss) at room temperature. The C-V and G/ω-V measurements have been carried out in the frequency range of 1 kHz to 1 MHz. The frequency dispersion in capacitance and conductance can be interpreted only in terms of interface states and series resistance. The N_ss can follow the ac signal and yield an excess capacitance especially at low frequencies. In low frequencies, the values of measured C and G/ω decrease in depletion and accumulation regions with increasing frequencies due to a continuous density distribution of interface states. The C-V plots exhibit anomalous peaks due to the N_ss and R_s effect. It has been experimentally determined that the peak positions in the C-V plot shift towards lower voltages and the peak value of the capacitance decreases with increasing frequency. The effect of series resistance on the capacitance is found appreciable at higher frequencies due to the interface state capacitance decreasing with increasing frequency. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under both reverse and forward bias were corrected for the effect of series resistance to obtain the real diode capacitance. Experimental results show that the locations of N_ss and R_s have a significant effect on electrical characteristics of MIS structures.     

Very low-noise Al/sub 0.3/Ga/sub 0.7/As/Ga/sub 0.65/In/sub 0.35/As/GaAs single quantum-well pseudomorphic HEMTs

AlGaAs/GaInAs/GaAs pseudomorphic HEMTs with an InAs mole fraction as high as 35% in the channel has been successfully fabricated. The device exhibits a maximum extrinsic transconductance of 700 mS/mm. At 18 GHz, a minimum noise figure of 0.55 dB with 15.0 dB associated gain was measured. At 60 GHz, a minimum noise figure as low as 1.6 dB with 7.6 dB associated gain was also obtained. This is the best noise performance yet reported for GaAs-based HEMTs.<>     

A 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode array

We report a 12 /spl times/ 12 In/sub 0.53/Ga/sub 0.47/As-In/sub 0.52/Al/sub 0.48/As avalanche photodiode (APD) array. The mean breakdown voltage of the APD was 57.9 V and the standard deviation was less than 0.1 V. The mean dark current was /spl sim/2 and /spl sim/300 nA, and the standard deviation was /spl sim/0.19 and /spl sim/60 nA at unity gain (V/sub bias/ = 13.5 V) and at 90% of the breakdown voltage, respectively. External quantum efficiency was above 40% in the wavelength range from 1.0 to 1.6 /spl mu/m. It was /spl sim/57% and /spl sim/45% at 1.3 and 1.55 /spl mu/m, respectively. A bandwidth of 13 GHz was achieved at low gain.     

Al/sub 0.3/Ga/sub 0.7/As/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) doped-channel field-effect transistors (DCFET's)

The properties of both lattice-matched and strained doped-channel field-effect transistors (DCFET's) have been investigated in AlGaAs/In/sub x/Ga/sub 1-x/As (0/spl les/x/spl les/0.25) heterostructures with various indium mole fractions. Through electrical characterization of grown layers in conjunction with the dc and microwave device characteristics, we observed that the introduction of a 150-/spl Aring/ thick strained In/sub 0.15/Ga/sub 0.85/As channel can enhance device performance, compared to the lattice-matched one. However, a degradation of device performance was observed for larger indium mole fractions, up to x=0.25, which is associated with strain relaxation in this highly strained channel. DCFET's also preserved a more reliable performance after biased-stress testings.<>     

Lanthanum diffusion in the TiN/LaOx/HfSiO/SiO2/Si stack

Band edge Complementary Metal Oxide Semiconductor (CMOS) devices are obtained by insertion of a thin LaO_x layer between the high-k (HfSiO) and metal gate (TiN). High temperature post deposition anneal induces Lanthanum diffusion across the HfSiO towards the SiO₂ interfacial layer, as shown by Time of Flight Secondary Ions Mass Spectroscopy (ToF-SIMS) and Atom Probe Tomography (APT). Fourier Transform Infrared Spectroscopy in Attenuated Total Reflexion mode (ATR-FTIR) shows the formation of La-O-Si bonds at the high-k/SiO₂ interface. Soft X-ray Photoelectron Spectroscopy (S-XPS) is performed after partial removal of the TiN gate. Results confirm La diffusion and changes in the La chemical environment.     

Highly linear Al/sub 0.3/Ga/sub 0.7/N-Al/sub 0.05/Ga/sub 0.95/N-GaN composite-channel HEMTs

We report an Al/sub 0.3/Ga/sub 0.7/N-Al/sub 0.05/Ga/sub 0.95/N-GaN composite-channel HEMT with enhanced linearity. By engineering the channel region, i.e., inserting a 6-nm-thick AlGaN layer with 5% Al composition in the channel region, a composite-channel HEMT was demonstrated. Transconductance and cutoff frequencies of a 1 /spl times/100 /spl mu/m HEMT are kept near their peak values throughout the low- and high-current operating levels, a desirable feature for linear power amplifiers. The composite-channel HEMT exhibits a peak transconductance of 150 mS/mm, a peak current gain cutoff frequency (f/sub T/) of 12 GHz and a peak power gain cutoff frequency (f/sub max/) of 30 GHz. For devices grown on sapphire substrate, maximum power density of 3.38 W/mm, power-added efficiency of 45% are obtained at 2 GHz. The output third-order intercept point (OIP3) is 33.2 dBm from two-tone measurement at 2 GHz.