A real-time curve tracer for the AC plasma display panel

A minicomputer-controlled system is used to automatically measure the wall charge transfer curve of a single cell in an ac plasma display panel. Curves can be plotted on a graphics display as fast as 5/s which allows real-time interaction with the user. The measurement technique is based on the ability to directly measure the wall charge from a single cell. The minicomputer controls the sustain voltage across the cell and obtains the resulting wall charge. It then does the tedious algebra needed to complete the transfer curve. The measured curves show numerous interesting effects. The influence of the state of the neighboring cells can clearly be seen. The duty factor of the sustain waveform has a strong influence on the transfer curve. An effect dependent on sustain frequency is presented that shows a transfer curve region with negative slope. The most interesting effect measured is a hysteresis in the transfer curve, in that a different curve is traced out as the cell goes from off to on than when it goes from on to off.     

Measurement of a plasma in the AC plasma display panel using RF capacitance and microwave techniques

The existence of a long-lived plasma in the gas volume is demonstrated by two techniques. By using a suitable RF frequency, the capacitance of plasma cells is shown to vary due to the production and decay of the plasma. In a special large-area cell constructed to minimize stray-capacitance problems, the plasma caused the capacitance to increase by a factor of 7 over the neutral value. This means that at the peak, the plasma filled about 6/7 of the discharge gap. By constructing a special-geometry plasma cell in the shape of a strip-transmission line, the microwave transmission properties were determined at 10 GHz. When the plasma is in the volume, the transmission is cut off. There is strong correlation between the capacitance variation and the microwave transmission variation. Depending on various conditions, the two techniques show the plasma to exist between 10 and 100 µs after the discharge-current peak. The plasma can be swept out of the volume by either positive- or negative-going applied voltage pulses. Thus the plasma is usually swept out upon the fall of the sustain voltage, especially when the sustain duty factor is less than 100 percent.     

Measurements of leakage currents and the capacitance of the storagecapacitor in a single DRAM cell

Methods of measuring leakage currents and the capacitance of the storage capacitor in a single DRAM cell have been developed for correlation with the electrode shape of the capacitor. In the circuit used for these measurements, the plate electrode of the storage capacitor is connected to the gate of the MOSFET which amplifies the voltage variations of the storage capacitor during the measurements. Here, only a conventional transistor parameter analyzer and a capacitance meter are required for the measurements. For the capacitance measurement, the linear region characteristics of the MOSFET are used to simplify the analysis. For the leakage current measurement, however, the subthreshold region characteristics of the MOSFET are used to enhance the accuracy of the measurement. The results show that the very low leakage currents (down to below 0.1 fA) and the capacitance (37.5 fF) of the storage capacitor can be measured accurately. Further, the leakage current-voltage characteristics of the storage capacitor are discussed by comparing with those of a large area planar capacitor whose structure is the same as the storage capacitor     

Simulation for capacitance correction from Nyquist plot of complex impedance–voltage characteristics

The impression of series resistance on unipolar semiconductor device’s capacitance–voltage spectrum is discussed by conventional impedance and admittance analysis, and it is shown that series resistance may cause large errors in capacitance–voltage data. It is shown that the existence of such errors can be deduced from suitable complex impedance measurement obtained during the capacitance–voltage measurement process and this information can be used to correct the distorted capacitance values. A theoretical analysis and computer simulation are presented in order to illustrate the nature of the problem and the technique by which accurate depletion region capacitance can be obtained.     

Electron transport self-shift display using an AC plasma panel

Using an electron transport mechanism, a self-shift display has been successfully implemented on an ac plasma panel providing higher resolution, higher shifting speed, and wider operating margins than previously obtained. The mechanism consists of a unidirectional and efficient transport of a large portion of electrons (generated during the display site discharge) to a neighboring OFF transfer site by a low transverse voltage. The process results in a large wall voltage build-up at the transfer site to switch its state from OFF to ON. The implemented electron transport self-shift display consists of a 7 × 128 site array of an Owens-Illinois 60 lines per inch panel where the 128 columns are driven by a four-phase driver. A resolution of one display site for every two electrodes and a shifting speed better than 600 characters per second have been successfully demonstrated. The ranges of the shifting voltages VDand VTare better than 15 V over a 10-V sustain range. The shifting operation also was successfully demonstrated on an 83 lines per inch panel with good operating margins.     

A useful modification of the technique for measuring capacitance as a function of voltage

Measurements of small signal capacitance as a function of applied bias voltage are widely used for the determination of information about metal-insulator-semiconductor (MIS) capacitors. The information that can be derived from the measurements includes interface-state density and flat-band charge density at the insulator-semiconductor (IS) interface, semiconductor doping, and charge stability under bias-temperature stress. A limitation on the use of this measurement method which has until now prevented its even more general application is the requirement that in order to determine Cs, the semiconductor space-charge capacitance, with reasonable accuracy the ratio of Csto CI, the insulating layer capacitance, must be ∼ 10. In the present work it is shown that a modification of the usual method can significantly relax this restriction and allow the accurate determination of Cswhen the ratio Cs/Cris as large as 100 or more, In fact, the inherent limit is no longer directly dependent on this ratio but on the noise level in the capacitance measurement. In some cases Cs/CI≥ 1 due to a thick insulating layer, A very large bias voltage is then required to span the capacitance range of interest; commercially available capacitance meters which typically have applied bias capabilities of ±600 V or less may be inadequate. A simple circuit modification has been employed to allow much larger bias voltages (up to ± 7 kV in the present Work) to be applied to the sample without alteration of or damage to the capacitance meter.     

Charge spreading and its effect on AC plasma panel operating margins

Like normal wall charges in an ac plasma panel, the spread charges from neighbor "on" cells to an "off" cell site can cause an increase or decrease in the required write voltage depending on the relative location of the write pulse with respect to sustain pulses. The net changes in write voltage can be accurately measured. The results obtained show that spread charges increase sharply with panel resolution and have a dominant influence over other priming effects on operating margin, e.g., to compensate for the wall voltage due to spread charges, an additional 15.5 V, or 10 percent of the voltage used to write an isolated cell, is required to write a cell which is located in the middle of a cluster of"on" cells on a high resolution 512-60 panel.     

Charge transport in an AC plasma panel

A transverse voltage applied between a display cellDand a transfer cellTon a standard 60 lines/inch ac plasma panel can simultaneously cause a previously ON cellDto fire and transport a large amount of electrons from cellDtoward cellT. The same transverse voltage combines with the voltage due to transported electrons to produce subsequent discharges which, initiated near cellT, grow rapidly as they propagate along the row toward cellD. A voltage pulse (≃sustain pulse), applied to cellT, will combine with the local row wall voltage to produce another sequence of discharges along the row. These discharges, initiated near cellD, gain intensity as they spread toward cellT. This dynamic process results in a large and controllable charge transfer between the display cellDand the transfer cellT, a key mechanism for shift address display. By reversing the polarity of the transverse voltage, ions also can be transported, but ion transport produces smaller charge transfer.     

A new process-variation-immunity method for extracting capacitancecoupling coefficients in flash memory cells

Overestimation of capacitance coupling coefficients in flash memory cells is encountered in the subthreshold slope method. By means of a two-parameters subthreshold current model I_D=I₀ exp[q(V_GB - nV_SB)/nkT], a mathematical formulation of the subthreshold swing ratio in the subthreshold slope method is constructed to isolate the measurement errors caused by process variations from the errors traditionally caused by bulk capacitance coupling. To minimize the effect of process variations, a new method is developed based on the model. In this method, the control gate voltage shift due to weak body effect is measured in flash memory cells in subthreshold, while the corresponding slope factor n is adequately deduced from threshold voltage versus source-to-substrate bias measurement in dummy devices. The corrected capacitance coupling coefficients show large improvements compared to the design values, and the updated errors are found to be close to that caused solely by bulk capacitance coupling. The method is also fast since only a small source-to-substrate bias of 0.1 V is needed for implementation of weak body effect, and thereby it can be used as an in-line monitor of capacitance coupling coefficients     

Application of the Shubnikov-de Haas oscillations in the characterization of Si MOSFET's and GaAs MODFET's

The Shubnikov-de Haas magnetoconductance oscillations were used to measure directly the gate-to-channel capacitance of Si MOSFET's and GaAs MODFET's, to detect the onset of parallel conduction in GaAs MODFET's, and to provide an approximate measure of channel length in sub-100-nm channel of Si MOSFET's. The measurements do not require knowledge of any device parameters, are immune to any gate parasitic capacitance, and are independent of source and drain series resistances. One needs to know only the magnetic field, the oscillation period (for gate-to-channel capacitance measurement), the gate voltage (for detection of the onset of parallel conduction), and the number of oscillation peaks (for the channel length characterization). Experimental results have shown that the characterization methods are accurate, and can be applied to FET's with sub-100-nm channel length.     

Scaling theory of liquid-crystal displays addressed by thin-filmtransistors

The proposed scaling theory for designing thin-film transistor/liquid-crystal displays (TFT/LCD's) addresses the need for a new design theory for fabricating TFT panels. A constant field is assumed, the same as for MOSFET scaling. A constant voltage is assumed based on the fact that the operational voltages of liquid-crystal cells are not easily scaled. Scaling is found to improve the gate delay and offset voltage characteristics in spite of the narrower busline width and the smaller pixel capacitance. The same improvements are observed even in larger, higher-resolution panels. This scheme to scale the pixel capacitance can be extended to an unloaded-pixel scheme in which there is no storage capacitance in the pixels. The trade-off in this scheme is between a short charging-time constant and a large aperture ratio, and a large voltage offset and a short discharging-time constant. The scaling theory is shown to be a valuable tool to design the next-generation TFT panels     

On-chip capacitance measurement circuits in VSLI structures

A precise capacitance measurement technique is described. This technique is based on a principle of capacitively divided ac voltage measurement. Details of the measurement procedure and test pattern configuration is also discussed. Utilizing the technique, precise capacitance measurements were carried out, which were practically difficult with direct measurements, and size effects of the small geometry capacitances were measured and evaluated. The technique was found to be practical and accurate, and besides, the test device can be integrated on an LSI chip, thus it appears to be very effective in VLSI development.     

电荷放大器对石英传感器动态特性的影响

用控制理论对压电石英传感器的等效电路、电压放大器、电荷放大器对压电式传感器动态特性的影响等进行了深入的分析与研究。通过对电压放大器与电荷放大器的系统传递函数的分析指出,压电电压测量系统可等效为1阶环节和2阶惯性环节。由于1阶系统的存在,导致系统不能测量直流信号和变化比较缓慢的信号。该电压测量系统的缺点可通过加电荷放大器来改善,此时压电电荷测量系统的稳态灵敏度为d/CF,它只依赖于电荷放大器的反馈电容,与石英晶体和连接导线的电容无关。从而指出为了充分利用石英传感器,应用时最好连接电荷放大器。     

Surface states at steam-grown silicon-silicon dioxide interfaces

A method of determining the energy distribution of surface states at silicon-silicon dioxide interfaces by using low-frequency differential capacitance measurements of MOS structures is described. Low-frequency measurements make it possible to determine the silicon surface potential as a function of MOS voltage directly from the experimental data without requiring knowledge of the Si doping profile. No graphical differentiations are required to determine the surface state density from the experimental curves, and errors introduced by uncertainties in the silicon doping density are reduced. Also, it is shown that the measurements can be used to determine the relative lateral uniformity in the characteristics of the oxide and interface under the MOS field plate. Nonuniformities can result in large errors in the surface-state density derived from MOS capacitance measurements. Measurements are presented and interpreted for both n- and p-type silicon samples prepared by bias-growing the oxide in steam.     

Cd1-x Zn x Se thin film electrodes: an electrochemical photovoltaic study

The interface between an n?Cd_1?x Zn _x Se semiconductor and an electrolyte redox couple is investigated through the capacitance–voltage, current–voltage and photovoltaic characteristics. A brief discussion is made on the properties of a semiconductor/electrolyte Schottky barrier with reference to the experiments performed. The observed results of the capacitance–voltage measurements in the dark are compared with the photovoltage measurements. The dependence of the dark current on the dark voltage for both forward and reverse bias is examined and explained. It is probable that the current–voltage characteristics are determined by the electrochemical kinetics in addition to the diode rectifier theory. The measurements of photovoltaic properties show a significant improvement in the cell performance after addition of Zn to CdSe (optimum at x = 0.3).     

State inversion of plasma panel cell

Two pulses applied in sequence to a cell of a plasma panel cause inversion of the state of the cell. The first, an inverting write pulse Vwi, narrower than a normal write pulse and positioned within the discharge recovery time ahead of a sustain pulse, can cause a cell to switch "on" in such a way that the cell wall voltage builds up to its steady-state value gradually over several sustain cycles. The second is a conventional erase pulse Ve. If the cell is initially "on," Vwihas no effect while Veinverts the cell to the "off" state. On the other hand, if the cell is initially "off," Vwicauses a low-level discharge such that the wall voltage is too low at the time Veis applied to the cell to cause a discharge, but the wall voltage keeps building up to a steady "on" state through a number of sustain cycles. Thus Vehas no effect and the cell remains "on." Using the state inversion, a blinking cursor has been successfully demonstrated on an 80 × 256 plasma panel. Negative image and bandwidth reduction in bilevel picture transmission could also be achieved with state inversion.     

Admittance and nonlinear capacitance of a multilayer metal-semiconductor structure

Nonlinear properties of capacitance and frequency dependence of admittance for a multilayer metal-semiconductor structure are studied theoretically. It is shown that admittance of such structure depends on the frequency of a small probe signal. The voltage dependence of capacitance measured using a low-frequency probe signal can be nonmonotonic. The behavior of the structure’s capacitance at a large amplitude of external signal is studied. After some time from the instant of switching-on of the high-frequency signal, the system is found in a steady state with certain charge of the metal layer and predefined capacitance of the system. In the steady state, the charge of metal and the capacitance do not depend on the instantaneous value of the voltage; rather, they are governed by the signal’s amplitude.     

Bridge measurement of tunnel-diode parameters

A specific bridge measurement technique is presented for measuring the important small-signal parameters of the tunnel diode at frequencies up to 100 Mc and at all significant operating levels. Particular attention is paid to the problem of biasing the tunnel diode to eliminate instability in the negative resistance region which would otherwise prevent significant measurements being made in this region. Requirements for stable bias circuits are analyzed in detail and specific criteria for stable operation given. A circle diagram method is presented which allows the significant parameters to be determined from a set of measurements made for a sequence of bias voltages, at a chosen frequency. From the results, curves of shunt capacitance and conductance as a function of bias voltage may be plotted. Measurements made using a Wayne Kerr Type B.801 VHF Admittance Bridge on a particular tunnel diode are presented. The experimentally determined capacitance vs voltage curve is found to agree closely with the theoretical curve of the normal junction diode, with no pecularities through the negative resistance region. Further results show that approximate parameter values may be obtained even when oscillatory or bistable behavior prevents satisfactory measurement in the negative resistance region.     

Application of junction capacitance measurements to the characterization of solar cells

The quasi-static capacitance-voltage ( C-V) technique measures the dependence of junction capacitance on the bias voltage by applying a slow, reverse-bias voltage ramp to the solar cell in the dark, using simple circuitry. The resulting C-V curves contain information on the junction area and base dopant concentration, as well as their built-in potential. However, in the case of solar cells made on low to medium resistivity substrates and having thick emitters, the emitter dopant profile has to be taken into account. A simple method can then be used to model the complete C-V curves, which, if the base doping is known, permits one to estimate the emitter doping profile. To illustrate the method experimentally, several silicon solar cells with different base resistivities have been measured. They comprise a wide range of areas, surface faceting conditions and emitter doping profiles. The analysis of the quasi-static capacitance characteristics of the flat surface cells resulted in good agreement with independent data for the wafer resistivity and the emitter doping profile. The capacitance in the case of textured surfaces is a function of the effective junction area, which is otherwise difficult to measure, and is essential to understand the emitter and space charge region recombination currents. The results indicate that the effective area of the junction is not as large as the area of the textured surface.     

Calibration Technique for Maximum Power Harvest of Passive Wireless Microsystems

A calibration technique for maximizing radio-frequency power harvest of passive wireless microsystems with a step-up transformer is proposed. We show that both the impedance and resonant frequency of the step-up transformer matching network can be adjusted by varying the capacitance of a shunt varactor placed at the secondary winding of the transformer to maximize power transfer from the antenna to the transformer and the output voltage of the transformer subsequently the power efficiency of the voltage multiplier. A low-power current-mode tuning technique and a maximum peak amplitude detection technique to allocate the optimal tuning capacitance at which the maximum power harvest exists are introduced. The transformer matching network has been designed in IBM CMRF8SF 130-nm 1.2-V CMOS technology, and its performance is validated using both simulation and on-wafer measurement results.