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基于串行单斜率积分的原理,提出了一种新型的像素级红外焦平面片上8位模数转换电路.设计了一个8×8像素阵列组成的完整读出电路芯片,并进行了版图设计和电路仿真.每个单元像素电路采用直接注入方式输入,输出与输入电流成正比的数字脉冲信号,经每列单元共享的计数器计数输出.采用独特的数字电路列共享结构,电荷注入补偿等技术,具有结构简单、面积小等特点.仿真及测试结果表明,该芯片能较好地完成红外焦平面信号读出及模数转换功能,单元面积80 μm×80 μm,单元功耗50 μW,量化等级达到8位,芯片实测量化误差小于4 LSB,帧速可达460 f/s. 相似文献
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针对SOI二极管型非制冷红外探测器,设计了一种新型读出电路(ROIC)。该电路采用栅调制积分(GMI)结构,将探测器输出电压信号转化为电流信号进行积分。设计了虚拟电流源结构,消除线上压降(IR drop)对信号造成的影响。电路采用0.35μm 2P4M CMOS工艺进行设计,5V电源电压供电。当探测器输出信号变化范围为0~5mV时,读出电路仿真结果表明:动态输出范围2V,线性度99.68%,信号输出频率5MHz,功耗116mW。 相似文献
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基于自偏置电流镜的CMOS红外焦平面读出电路 总被引:1,自引:0,他引:1
针对高精度红外焦平面阵列应用设计了一种具有高注入效率、大动态范围、稳定的探测器偏压、小面积和低功耗的自偏置电流镜注入CMOS读出电路.所设计的电路结构包括一种由自偏置的宽摆幅PMOS共源共栅电流镜和NMOS电流镜构成的反馈结构读出单元电路和相关双采样电路.对所设计电路采用Chartered 0.35 μm CMOS工艺进行了流片.测试结果显示:电路线性度达到了99%,探测器两端偏压小于1mV.电路输入阻抗近似为0,单元电路面积为10μm×15μm,功耗小于0.4μW.电量存储能力3108电子.测试结果表明:电路功能和性能都达到了设计要求. 相似文献
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Philip Simpson 《电子设计技术》2003,10(1):65-66
当一个由处理器控制的装置必须可靠工作时,设计师往往不会选择依靠一种看门狗电路结构,而愿意选择使处理器定期复位的方式。在小功率系统中,这种定期复位电路会消耗系统电流预算的大部分,也可能在低电压下无法工作。图1所示的电路能产生一个宽度为100μS的下降沿复位脉冲。该电路消耗不到1μA的工作电流,并可由1.8~5V电源供电,而输出脉冲周期变化很小。该电路是由常规张驰振荡器改进而成的,它在输出端由一个微分器和二极管箝位,以便产生 相似文献
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针对光电探测器的光电流信号弱、变化范围大的特点,设计了一种全新的检测光电流信号的跨阻放大器(TIA)电路结构,其检测电流信号范围为1.6 μ上A~1.6 mA,动态电流检测范围达到60 dB.通过在电路内部设计出两个增益可调、增益段不同的TIA,分别处理光电流的小电流段(1.6~50 μA)和大电流段(50 μA~1.6 mA),增益可调范围为56~96 dBΩ;通过外置输出电压饱和检测信号,选择所需工作的TIA及其增益段.该电路采用0.18 μm标准CMOS工艺的PDK进行电路设计、版图设计和仿真验证等.测试结果表明:在检测电流为1.6 μA时,输出电压为95 mV;检测电流为1.6mA时,输出电压为915 mV,与仿真结果相一致.电路瞬态特性良好,上升时间为5~10 ns,3.3V电压下功耗小于2 mW,各指标满足设计要求. 相似文献
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扫描式红外成像传感器在遥测遥感、卫星成像等远距离成像领域具有广泛的应用。为了缓解信噪比相对较低而影响图像质量的问题,提出了一种时间延时积分(TDI)型读出电路。该读出电路由电容跨阻放大器(CTIA)像素电路阵列、并行TDI电路、多路开关选择电路和输出缓冲器等组成。为实现对宽动态范围光电流的处理,CTIA电路设计有多档可选增益,且非线性度小于0.3%。该读出电路采用0.35 μm CMOS工艺设计与制造,芯片面积约为1.3 mm×20 mm,采用5 V电源时功耗小于60 mW。为了评估1024×3 TDI读出电路的功能,采用了对TDI输入端注入不同电压激励的方式进行测试,测试结果验证了所提出的设计方案。 相似文献
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在分析电容式MEMS麦克风工作原理的基础上,提出了一种用于电容式MEMS麦克风的读出电路.该读出电路包括低极点频率的高通滤波器和低噪声单位增益缓冲器,高通滤波器用来读出MEMS麦克风在声压作用下产生的小信号,单位增益缓冲器用来隔离高通滤波器和后续信号处理电路,并提供较大的驱动能力.仿真结果表明,当电源电压在1.2~3.6V之间时,读出电路都可以正常工作,且静态电流小于60 μA,等效输入噪声为5.2 μV,电压增益大于-1.56 dB(83.6%).由于消除了失调电压的影响,电路可以处理幅度范围为50 μV~200 mV的小信号(参考X-FAB 0.35 μm CMOS工艺). 相似文献
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Jae‐Mun Oh Byung‐Do Yang Hyeong‐Ju Kang Yeong‐Seuk Kim Ho‐Yong Choi Woo‐Sung Jung 《ETRI Journal》2015,37(5):961-971
This paper proposes a 250 mV supply voltage digital low‐dropout (LDO) regulator. The proposed LDO regulator reduces the supply voltage to 250 mV by implementing with all digital circuits in a 0.11 μm CMOS process. The fast current tracking scheme achieves the fast settling time of the output voltage by eliminating the ringing problem. The over‐voltage and under‐voltage detection circuits decrease the overshoot and undershoot voltages by changing the switch array current rapidly. The switch bias circuit reduces the size of the current switch array to 1/3, which applies a forward body bias voltage at low supply voltage. The fabricated LDO regulator worked at 0.25 V to 1.2 V supply voltage. It achieved 250 mV supply voltage and 220 mV output voltage with 99.5% current efficiency and 8 mV ripple voltage at 20 μA to 200 μA load current. 相似文献
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A high-performance CMOS readout integrated circuit (ROIC) with a new temperature and power supply independent background current
and dark current suppression technique for room-temperature infrared focal plane array applications is proposed. The structure
is composed of an improved switched current integration stage, a new current-mode background suppression circuit, and a high
linearity, high voltage swing output stage. An experimental readout chip has been designed and fabricated using the Chartered
0.35 μm CMOS process. Both the function and performance of the proposed readout circuit have been verified by experimental
results. The test results show that the detector bias error in this structure is less than 0.1 mV. The input resistance is
close to an ideal value of zero, and the injection efficiency is almost 100%. The output voltage linearity of the designed
circuit is more than 99%. The background suppression level is tunable between 8 nA–1.5 μA, and the background suppression
uniformity is as high as 100%. A unit-cell occupies a 10 μm × 15 μm area and consumes less than 0.07 mW power. 相似文献
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设计并实现了一种动态补偿、高稳定性的LDO.针对LDO控制环路稳定性随负载电流变化的特点,给出一种新颖的动态补偿电路.这种补偿电路能很好地跟踪负载电流的变化,从而使控制环路的稳定性几乎与负载电流无关.设计采用CSMC 0.5μm标准CMOS工艺,利用Cadence的EDA工具完成电路设计、版图绘制和流片测试,最终芯片面... 相似文献
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Tsukude M. Kuge S. Fujino T. Arimoto K. 《Solid-State Circuits, IEEE Journal of》1997,32(11):1721-1727
A charge-transfer presensing scheme (CTPS) for 0.8-V array operation with a 1/2 Vcc bit-line precharge achieves a five times larger readout voltage and 40% improvement in sensing speed compared with conventional sensing schemes. Operation over a 1.2- to 3.3-V range is achieved. A nonreset row block control scheme (NRBC) for power-consumption improvement in data-retention mode is proposed which decreases the charge/discharge number of the row block control circuit. By combining CTPS and NRBC, the data-retention current is reduced by 75% 相似文献
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The diode infrared focal plane array uses the silicon diodes as a sensitive device for infrared signal measurement. By the infrared radiation, the infrared focal plane can produces small voltage signals. For the traditional readout circuit structures are designed to process current signals, they cannot be applied to it. In this paper,a new readout circuit for the diode un-cooled infrared focal plane array is developed. The principle of detector array signal readout and small signal amplification is given in detail. The readout circuit is designed and simulated by using the Central Semiconductor Manufacturing Corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor transistor (CMOS) technology library. Cadence Spectre simulation results show that the scheme can be applied to the CMOS readout integrated circuit (ROIC) with a larger array, such as 320×240 size array. 相似文献
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A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage... 相似文献
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采用无运放电路结构,通过改进反馈环路和调整电阻的方法,设计了一种低电压低功耗的带隙基准电压源.相比传统有运放结构,电路芯片面积更小和具有更低的电流损耗,并且大部分电流损耗都用于产生输出电压.基于CSMC 0.5 μmCMOS工艺对所研制带隙基准电压源进行流片,测试结果表明,当电源电压大于0.85 V时,能够产生稳定的输... 相似文献
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本文提出了一种不受寄生电容影响的适用于电容式传感器的全对称电容电压转换电路。通过引入参考支部实现了对称的读出电路结构,线性输入的范围从而得到增大,两个运放的系统失调也相互抵消,共模点的噪声干扰和偶次谐波得到了抑制。窄波技术的运用进一步减小了运放失调和闪烁噪声的影响。Verilog-A模型的容抗管用来模拟真实的可变待测电容。仿真结果表明该电路的输出电压能够准确的响应待测电容在1KHz频率下的变化。该芯片采用片上金属绝缘金属电容阵列来进行测试。测试结果表明电路的灵敏度为370mV/pF,非线性误差在1%以下,功耗为2.5mW,该电路可以响应由FPGA控制的每隔1ms变化的电容传感阵列。 相似文献