基于FT-2000/4的全国产平板式加固计算机设计

设计了一种基于飞腾FT-2000/4处理器的全国产平板式加固计算机,详细介绍了平板式计算机的主板架构、硬件设计、软件设计和结构设计,选用国产电子元器件,配合以国产固件、操作系统,实现了计算机的100%自主可控,有力地保障了信息安全。通过优化整机布局、结构设计,最大限度地降低了计算机的重量和体积,提高了使用的便携性和舒适性。同时考虑高低温、淋雨、盐雾、霉菌等环境试验要求,可满足军用室内、野外、车载、舰载等各种应用场景需求。     

基于低代码思想的可视化并行计算框架设计

先进装备的新型信息处理平台采用高性能多核处理器为核心的一体化架构,来满足高性能和智能化需求。为了支撑密集计算任务,需要并行计算框架来解决多核同步、负载均衡、任务调度、数据分发等并行计算应用难题。然而,现有的并行计算框架多为基于Linux的开源框架,不支持国产多核处理器;同时,基于并行计算框架的编程方式与传统的以控制算法为中心的结构化编程思路不同,对于习惯了C/C++编写串行程序的用户,基于并行计算框架编程面临许多难题。针对上述问题,在解决国产多核处理器操作系统并行计算框架适配问题的同时,基于低代码设计思想,研究简化并行计算框架编程方法、提升并行应用编程效率的技术途径,通过可视化组件配置与代码自动生成的方式,真正地降低并行编程难度,充分发挥国产多核处理器的并行计算效能。     

DVB-S卫星资料共享分发系统设计与实现

介绍了Visual Studio.net 2008开发环境下,基于Windows平台和SQL server 2000数据库的DVB-S卫星下发产品资料共享分发管理系统开发,包括数据库设计、功能模块划分、数据流程等,并分析总结了各个模块设计的关键技术。     

基于ATCA架构的可重构通信处理机设计

随着数据通信的飞速发展,各种业务需求日益剧增,基于先进电信计算机架构(ATCA)平台,选择可重构的嵌入式系统处理机就显得非常有必要。结合ATCA架构的特点,选择MPC8548E处理器作为处理机,提出了基于1000M以太网和PCI-E数据交互的通信系统模型,设计并实现了一种可重构的通信系统处理机,为基于ATCA架构的电信产品提供了灵活的应用选择。测试结果表明,该处理机无论在电气特性方面,还是在数据的处理能力方面都达到了业内相对领先的地步。     

通信与网络

可降低时钟树EMI的扩频时钟合成器；高密度传输多路复用器与映射方案；提供10Gbps数据包处理能力的ATCA模块；专为IMS优化的ATCA产品；端到端GPON解决方案；支持10Gbps速率的流量控制管理多队列器件；经验证面向通信和嵌入式应用的平台；先进交换数据通道交互解决方案。     

基于微能源网的物联网管理平台设计

文章以微能源网优化运行系统为研究背景,设计了一种基于数字信号处理器(DSP)的微能源网物联网管理平台。文章简述了监控管理平台以DSP为控制核心的主控模块、数据采集模块、网络通信等硬件设计;详细介绍了软件设计流程和相应控制策略,系统控制策略包括并网和离网;通过软件设计搭建虚拟管理平台LabVIEW,将系统采集数据接入物联网云平台,达到实现远程监控的目标。结果表明,物联网监控管理系统具有良好的实用性,便于系统的管理和故障排查,确保管理平台的稳定运行。     

面向缓存网络内容分发的非正交传输策略研究

面向无线缓存网络的内容分发场景，设计了一种两阶段自适应非正交/正交多址接入传输方案。针对该方案，提出了一种高可靠性用户调度策略，并通过理论分析得出了中断概率的解析表达式及其高信噪比下渐近表达式。分析结果表明，该策略可获得满空间分集增益。仿真结果表明，与基于瞬时信道状态信息的调度策略、随机调度策略以及传统的正交多址接入传输策略相比，所提策略可通过获取空间分集增益，实现优于现有策略的内容分发可靠性。     

业界动态

博通发布高密度100G交换解决方案近日,博通宣布推出全球密度最高的100GbE交换解决方案BCM88650系列,该芯片基于高密度交换平台设计,可以让以太网交换机实现对4000个100GbE端口的支持。据悉,该产品系列具有极高的集成度,能在一片芯片上兼具交换矩阵、网络接口、包处理器、流量处理器等4大模块,实现了     

基于龙芯2F的国产处理器平台在路由器中的设计实现

高性能处理器(CPU)作为路由器设备的核心部件之一,主要用于实现路由器设备的控制及协议处理功能。对核心部件CPU采用了国产的龙芯2F处理器及与之相适配的中标麒麟操作系统,构建了国产处理器平台,应用到路由器设备中,解决了长期以来路由器设备对国外处理器的依赖,提高了路由器设备的安全可靠性,实现了路由器设备在硬件、软件的自主可控。对国产处理器平台进行了简要介绍,并结合实例验证了国产处理器平台在路由器设备中的设计方案正确可行,能够满足路由器的需要,可以进行推广应用。     

面向多处理器的内网计算机BIOS口令集中管理机制研究

随着自主可控计算机产业链的不断完善,大量国产计算机终端已在企事业单位应用.BIOS口令是计算机安全管理的第一道门户,如何在异构处理器和多种操作系统并存环境下,对内网计算机终端BIOS口令进行安全管理成为迫切需要解决的问题.通过设计基于固件的BIOS口令集中管理系统总体框架,融合终端自动发现、BIOS口令自适应统一更新等...     

基于LabVIEW的跳频组件测控平台研究

为了满足跳频组件研制过程的测控需求,通过对跳频组件的工作原理和测控需求的分析,提出了基于计算机控制的测控平台的实现方案,研究了测控平台的设计原理、硬件结构和软件设计流程,最后在LabVIEW环境下开发出了针对具体跳频类组件应用的测控平台.实验证明,该测控平台的应用提高了组件的调试、测试效率,且缩短了组件的开发周期,具有很好的推广应用价值.     

空时二维雷达信号处理机的系统设计

针对雷达信号处理算法复杂、数据量大、数据传输速度高的特点,本文介绍一种基于ADSP-TS101通用信号处理板的设计,并以此处理板构成了空时二维雷达信号处理信号机.此处理板具有可重构性和可扩展性,简单的扩展或适当增加此模块的数目即可满足不同的雷达信号处理要求.     

一个低代价的完全自适应路由器设计

互连网络路由器是ＭＰＰ系统的关键器件，其性能优劣直接影响系统性能，本文在ｍｅｓｈ结构上，针对完全自适应器由算法实现难度较大的问题，在性能、低价和实现复杂性 进行合理折衷，给出了一个代价低、自适应性强的完全自适应路由算法ＬＣＦＡＡ，对传统的虫孔路由切换技术进行改进，提出了弹性虫孔路由切换技术，并采用基于虚通道的综合流控策略，设计了一个简洁高交的完全自适应路由器ＬＦＲ，其逻辑在ＸｉｌｉｎｘＸＡＣＴ的Ｃ     

A self‐adaptive load‐dispatching control framework for device data accessing in IoT‐based systems

The Internet of things (IoT) information system plays important roles in disposing of huge volumes of real‐time service requests from heterogeneous devices, targeting for different complex application requirements. Load‐dispatching control (LDC) is a key problem to be solved for devices accessing concurrently in cluster systems. Self‐adaptive LDC optimizes the resource allocation to ensure no overloading node, thus, improving the performance of IoT systems. This paper focuses on adaptive dispatching control problem in IoT information system. First, a device data access platform is proposed for reducing the load imbalance and improving the efficiency of data processing. Then, we propose a processing capability prediction model to evaluate the system performance. On the basis of the model, we present a practical self‐adaptive LDC framework with a self‐adaptive control strategy and a load dispatching method. Finally, a case study is given to verify the framework and the control strategy. Experimental results show that the proposed strategy can meet the requirements of dynamic load balancing with the ability to avoid the load imbalance problem, and the LDC‐based device access platform can process data accessing effectively and ubiquitously.     

Gbps试验系统中高速串行接口的设计与实现

介绍Gbps无线通信试验系统中高速串行数据接口的设计与实现。按照Gbps无线通信试验系统对高速串行数据的传输要求,数据传输速率超过1 Gb/s,在基于Xilinx IP core技术上对单板上的FPGA进行逻辑设计,实现了符合系统要求的高速串行数据接口。在系统实际调试中,通过ATCA机箱背板进行数据传输,获得了高达Gbps的数据吞吐速率且传输误码率低于10-14。     

Scalable Linear Array Architecture with Data-Driven Control for Ultrahigh-Speed Vector Quantization

Current and future requirements for adaptive real-time image compression challenge even the capabilities of highly parallel realizations in terms of hardware performance. Previously proposed linear array structures for full-search vector quantization do not offer scalability and adaptivity in this context, because they require separate data/control pins for dynamically updating the codevectors and complicated interlock mechanisms to ensure that the regular data flow is not corrupted as a result of updates. We explore the design space for full-search vector quantizers and propose a novel linear processor array architecture in which global wiring is limited to clock and power supply distribution, thus allowing high-speed processing in spite of only limited communication with the host via the boundary processors. The resulting fully pipelined design is not only area-efficient for VLSI implementation but is also readily scalable and offers extremely high performance.     

Radio Network Aggregation for 5G Mobile Terminals in Heterogeneous Wireless and Mobile Networks

This paper provides a novel design concept for advanced mobile multi interface terminals with radio network aggregation capability and enhanced quality of service (QoS) provisioning for multimedia services (voice, video and data) in heterogeneous wireless and mobile networks. A new module is established which provides the best QoS and lowest cost for any given multimedia service by using simultaneously all available wireless and mobile access networks for a given traffic flow. This novel adaptive QoS module with adaptive QoS routing algorithm is called advanced QoS routing algorithm (AQoSRA), which is defined independently from any existing and future radio access technology. The performance of our proposal is evaluated using simulations and analysis with multi-interface mobile stations with AQoSRA within, carrying multimedia traffic in heterogeneous mobile and wireless environment with coexistence of multiple Radio Access Technologies, such as 3G, 4G as well as future 5G radio access networks. The analysis of the proposed framework for radio networks aggregation in advanced mobile terminals has shown overall better performances regarding the achievable throughput and multimedia access probability in heterogeneous wireless and mobile environment.     

动载体光电稳定平台伺服控制系统设计

基于数字控制器TMS320F28335和驱动器MSK4226模块,利用光纤陀螺作为惯性空间角速率反馈传感器,完成了一种动载体光电稳定平台伺服控制系统的硬件和软件设计.详细介绍了硬件设计要求和原则、实现方法,分析了控制软件需求,设计流程,控制周期.测试结果达到预期要求,并将该系统应用于实际稳定平台设计中.     

红外偏振摄像机动目标检测跟踪系统（特邀）

基于红外偏振摄像的机动目标检测跟踪系统对实时性要求较高,而且在野外场景下需要具备低功耗的特点。FPGA具有并行计算的特性,能够极大的提高系统吞吐量和处理数据速度,能够满足实时性的要求,因此一种基于FPGA的目标检测跟踪系统被设计出来并得以实现。在硬件开发平台上采用模块化以及软硬件协同设计的方式,将具有不同计算特点的任务分别在PS端（ARM）以及PL端（FPGA）实现,其中PL部分负责部分算法的加速、FPGA和ARM处理器之间数据传输以及HDMI等接口逻辑控制等,PS部分负责实现较为复杂的检测跟踪算法,以及负责控制FPGA端的各个模块。最后,对目标检测跟踪系统进行实验测试和分析,给出系统的硬件资源消耗及功耗,结果表明该目标检测跟踪系统能够满足实时性的要求,并且具备低功耗的特点。     

Data Memory Subsystem Resilient to Process Variations

As technology scales, more sophisticated fabrication processes cause variations in many different parameters in the device. These variations could severely affect the performance of processors by making the latency of circuits less predictable and thus requiring conservative design approaches. In this paper, we use Monte Carlo simulations in addition to worst-case circuit analysis to establish the overall delay due to process variations in a data cache sub-system under both typical and worst-case conditions. The distribution of the cache critical-path-delay in the typical scenario was determined by performing Monte Carlo simulations at different supply voltages, threshold voltages, and transistor lengths on a complete cache design. In addition to establishing the delay variation, we present an adaptive variable-cycle-latency cache architecture that mitigates the impact of process variations on access latency by closely following the typical latency behavior rather than assuming a conservative worst-case design-point. Simulation results show that our adaptive data cache can achieve a 9% to 31% performance improvement in a superscalar processor, on the SPEC2000 applications studied, compared to a conventional design. The area overhead for the additional circuits of the adaptive technique has less than 1% of the total cache area. Additional performance improvement potential exists in processors where the data cache access is on the critical path, by allowing a more aggressive clock rate.