共查询到19条相似文献,搜索用时 171 毫秒
1.
2.
随着系统数据速率的提高,时钟抖动分析的需求也在与日俱增.在高速数据链路中,时钟分配器的时钟偏斜会影响系统的整体性能.分析了相位噪声和时钟抖动的对应关系,通过时域到频域的转换,实现了时钟偏斜参数的高精度测量.以一款时钟分配器为例,进行了实际测试验证. 相似文献
3.
4.
5.
随着广电系统双向网络改造的完成,视频类业务的多样化运营,广电系统网络中的相关设备对于时钟同步信息的需求越来越高。本文为了解决广电系统网络设备类型多样,设备分层架构组网的特点,基于广电系统接收GPS时钟作为精确时钟源的特点,使用NTP协议完成全网部署时钟源同步的方案。 相似文献
6.
7.
8.
针对5G智能电网的高精度时钟同步需求,提出一种主从节点时钟在线实时同步方法,并建立其数字实现模型。该方法采用一种由时差测量、时钟状态估计、环路滤波器和全数字时钟生成单元构成的时钟反馈控制环路。基于IEEE1588精确时间同步协议完成主从节点间的时差测量;根据时钟模型,建立时钟状态方程和观测方程,采用卡尔曼滤波对时钟状态进行估计;将时钟相位误差、频率误差作为一阶FLL辅助的PLL环路滤波器输入;环路滤波器输出控制量驱动调节从节点全数字时钟生成,以与主节点时钟保持在线实时同步。仿真结果表明,主从节点通信载噪比在65~95 dBHz范围内变化时,可实现主从节点间ns级的时钟同步精度。 相似文献
9.
在这篇文章中我们提出了一种用于突发方式系统的时钟恢复技术,它完成时钟相位恢复,突发同步和定时告警产生的功能。 相似文献
10.
为了解决电容充放电放大电路测量时间间隔的不稳定,采用复杂可编程芯片FPGA设计实现精密时间间隔的测量。FPGA的锁相环(PLL)电路得到高频时钟,时钟管理器(DCM)实现高速时钟移相,内插时钟得到高精度时间测量。通过在光电回波脉冲时间间隔测量系统中验证,该设计可以得到200ps的时间间隔测量精度。采用FPGA芯片设计的数字化测量系统,具有集成度高,性能稳定,抗干扰强,设计方便等优点,能广泛应用于科研和生产中 相似文献
11.
Jitter optimization based on phase-locked loop design parameters 总被引:1,自引:0,他引:1
This paper investigates the effects of varying phaselocked loop (PLL) design parameters on timing jitter. The noise due to voltage-controlled oscillator (WO), input clock and buffering clock are considered. First, a closed-form equations are derived that relate PLL output clock jitter to parameters of a second-order PLL, i.e., damping factor and bandwidth. Then the second-order analysis is extended to a third-order PLL with inherent feedback/sampling delay. The sensitivity study clearly illustrates how to select design parameters to obtain minimum output jitter. To verify the analysis experimentally, a digitally tunable PLL architecture is designed and fabricated that allows independent adjustment of loop parameters. The design not only demonstrates the agreement between analysis and theory, but also shows an architecture that minimizes jitter. 相似文献
12.
Hangbiao Li Bo Zhang Ping Luo Pengfei Liao Junjie Liu Zhaoji Li 《International Journal of Electronics》2013,100(3):462-475
A compact all-digital phase-locked loop (C-ADPLL) based on symmetrical binary frequency searching (BFS) with the same circuit is presented in this paper. The minimising relative frequency variation error Δη (MFE) rule is derived as guidance of design and is used to weigh the accuracy of the digitally controlled oscillator (DCO) clock frequency. The symmetrical BFS is used in the coarse-tuning process and the fine-tuning process of DCO clock frequency to achieve the minimum Δη of the locked DCO clock, which simplifies the circuit architecture and saves the die area. The C-ADPLL is implemented in a 0.13 μm one-poly-eight-metal (1P8M) CMOS process and the on-chip area is only 0.043 mm2, which is much smaller. The measurement results show that the peak-to-peak (Pk-Pk) jitter and the root-mean-square jitter of the DCO clock frequency are 270 ps at 72.3 MHz and 42 ps at 79.4 MHz, respectively, while the power consumption of the proposed ADPLL is only 2.7 mW (at 115.8 MHz) with a 1.2 V power supply. The measured Δη is not more than 1.14%. Compared with other ADPLLs, the proposed C-ADPLL has simpler architecture, smaller size and lower Pk-Pk jitter. 相似文献
13.
针对高速(Gbit/s)串行数据通信应用,提出了一种混合结构的高速时钟数据恢复电路。该电路结构结合鉴频器和半速率二进制鉴相器,实现了频率锁定环路和相位恢复环路的同时工作。和传统的双环路结构相比,在功耗和面积可比拟的前提下,该结构系统的复杂度低、响应速度快。电路采用1.8 V,0.18μm CMOS工艺流片验证,测试结果显示在2 Gbit/s伪随机数序列输入情况下,电路能正确恢复出时钟和数据。芯片面积约0.5 mm~2,时钟数据恢复部分功耗为53.6 mW,输出驱动电路功耗约64.5 mW,恢复出的时钟抖动峰峰值为45 ps,均方根抖动为9.636 ps。 相似文献
14.
Bo Ye 《Microelectronics Journal》2010,41(7):411-416
This paper presents a wide-range all digital delay-locked loop (DLL) for multiphase clock generation. Using the phase compensation circuit (PCC), the large phase difference is compensated in the initial step. Thus, the proposed solution can overcome the false-lock problem in conventional designs, and keeps the same benefits of conventional DLLs such as good jitter performance and multiphase clock generation. Furthermore, the proposed all digital multiphase clock generator has wide ranges and is not related to specific process. Thus, it can reduce the design time and design complexity in many different applications. The DLL is implemented in a 0.13 μm CMOS process. The experimental results show that the proposal has a wide frequency range. The peak-to-peak jitter is less than 7.7 ps over the operating frequency range of 200 MHz-1 GHz and the power consumption is 4.8 mW at 1 GHz. The maximum lock time is 20 clock cycles. 相似文献
15.
Multiphase clock generators are conventionally implemented with a feedback loop. This paper presents a non-feedback approach to generate multiphase clocks. A simple architecture of direct phase interpolation is proposed, in which the edges of two phase-adjacent signals are used to control the discharge (or charge) of two capacitors respectively, producing time-overlapped slopes. A resistor chain connected to the two capacitors is used to interpolate a number of new slopes in between. The generated phase resolution depends on the number and ratios of resistors thus is not limited by an inverter delay. Based on this architecture, a multiphase clock generator is developed. In addition, a phase error averaging circuit is used to correct interphase errors. The multiphase clock generator has been fabricated in a 0.35 m, 3.3 V CMOS process. The measured performance shows it can produce 8 evenly spaced clock signals in one input clock period and work in an input clock range from 300 MHz to 600 MHz. The measured maximum jitter performance is rms 6.8 ps and peak-to-peak 47 ps, respectively. 相似文献
16.
A semidigital dual delay-locked loop 总被引:1,自引:0,他引:1
This paper describes a dual delay-locked loop architecture which achieves low jitter, unlimited (modulo 2π) phase shift, and large operating range. The architecture employs a core loop to generate coarsely spaced clocks, which are then used by a peripheral loop to generate the main system clock through phase interpolation. The design of an experimental prototype in a 0.8-μm CMOS technology is described. The prototype achieves an operating range of 80 kHz-400 MHz. At 250 MHz, its peak-to-peak jitter with quiescent supply is 68 ps, and its jitter supply sensitivity is 0.4 ps/mV 相似文献
17.
全数字延时锁定环及其应用 总被引:4,自引:0,他引:4
介绍了一种区别于锁相环(PLL)和基于压控延迟线(VCDL)的延时锁定环(DLL)、全部由纯数字电路实现的DLL电路.该电路用于消除时钟时延,全数字的结构使其无条件稳定,不会累积相位误差,而且具有良好的噪声敏感度、较低的功耗和抖动性能.使其在时延补偿和时钟调整的应用中具有优势,并可全部嵌入单个芯片中.文中分析了全数字DLL的工作原理及其结构,给出了其在现场可编程门阵列(FPGA)中的应用. 相似文献
18.
Ching-Che Chung Chen-Yi Lee 《Solid-State Circuits, IEEE Journal of》2003,38(2):347-351
An all-digital phase-locked loop (ADPLL) for high-speed clock generation is presented. The proposed ADPLL architecture uses both a digital control mechanism and a ring oscillator and, hence, can be implemented with standard cells. The ADPLL implemented in a 0.3-/spl mu/m one-poly-four-metal CMOS process can operate from 45 to 510 MHz and achieve worst case frequency acquisition in 46 reference clock cycles. The power dissipation of the ADPLL is 100 mW (at 500 MHz) with a 3.3-V power supply. From chip measurement results, the P/sub k/-P/sub k/ jitter of the output clock is <70 ps, and the root-mean-square jitter of the output clock is <22 ps. A systematic way to design the ADPLL with the specified standard cell library is also presented. The proposed ADPLL can easily be ported to different processes in a short time. Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable for system-on-chip applications. 相似文献
19.
Kishine K. Ishihara N. Takiguchi K. Ichino H. 《Solid-State Circuits, IEEE Journal of》1999,34(6):805-812
A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LAN's and WAN's. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs 相似文献