天然气船培训仿真软件的开发

介绍了天然气船培训仿真软件的程序框架,在VisualC＋＋开发平台上,采用了多线程、动态链接库、无缓冲绘图等计算机仿真关键技术和方法,设计并实现了天然气船培训仿真软件,使得对船员的教学和培训达到与在实船上一样的培训效果。     

IC卡读写新招:利用PC机打印机接口

本文介绍用ＰＣ机打印妆口实现对存储式ＩＣ卡的读写电路,以及实现ＩＣ卡读写操作软件流程图。该软件用ＶｉｓｕａｌＣ＋＋语言编写,以动态链接库的形式供其它应用程序调用。     

动态链接库开发技术研究与应用

如何开发一个适用于具体应用的动态链接库是每一个开发人员所必须面对的问题,基于Visual C 开发平台,本文详细了各种类型动态链接库的特点和各自的实现细节,阐述了VC＋＋中,DLL编程的基本流程和技术。     

Win32环境下动态链接库（DLL）编程

介绍在Win32环境下用Visual C＋＋进行动态链接库（DLL）编程方法,以将独立的程序模块创建为较小的DLL（Dynamic Linkable Library)文件,并可对它们单独编译和测试。增加了程序设计人员在Windows环境中开发软件的灵活性,使软件与Windowe系统达到了优化结合。     

基于VC++ 6.0的GPIB仪器控制实现方法

利用VC＋＋6．0控制GPIB仪器的程序直观、可读性较强,但需通过算法对回读的仪器波形进行解析。LabVIEW8．0具有自动解析波形的功能。为了更好地利用两种软件的优势,提高编程效率,本文提出了在VC＋＋6．0境下利用Agilent VISA transition library与LabVIEW生成的动态链接库共同对GPIB仪器进行控制的方法,并举例说明该方法在频谱仪控制中的应用。     

基于不同开发工具的多应用程序间数据交互的研究

介绍了用Visual C＋＋创建可供Power Builder调用的动态链接库的技术和方法．适用于多个应用程序间的数据交互,对于采用不同开发工具进行并行开发的情况有一定的实用价值。     

利用JNI技术用JAVA实现Ping功能

本文利用JNI技术使JAVA与C／C＋＋的动态链接库dll进行通信和调用，用JAVA语言实现了Ping操作。该模块最终可以应用到JAVA语言实现的网管系统中。     

利用CVI,VC环境驱动数据库的一种简单方法

介绍了一种方法，用于在Visual C^ 6．0环境下构建驱动Access的DLL动态链接库，然后在LabWindows／CVI环境下调用此动态链接库，从而实现了测控软件的简单数据库驱动。     

基于单片机USB接口的PC主机驱动程序和应用程序设计

介绍了与51单片机USB接口的PC主机在Windows环境下软件设计过程。驱动程序由DriverStudio生成,动态链接库和应用程序分别采用Visual C＋＋和Visual Basic编写。实现了PC机与单片机之间通过PDIUSBD12芯片进行数据通讯的功能。     

基于AVR USB接口的温度测量系统硬件及上位机设计

给出了利用ATMEGA8的USB通信端口与计算机进行连接来实现温度监控与显示的具体方法。同时利用VC＋＋结合AVRUSB动态链接库,给出了用AVRUSB实现软USB,从而完成USB数据传输的系统硬件及上位机软件的设计方法。     

在MFC DLL中和Windows 32 DLL中使用资源的比较

主要比较了DLL在MFC中和在Windows 32中使用资源之间的差异，详细介绍了在Windows 32 DLL中使用资源和在MFCDLL中使用的具体方法，讲述了按照MFC库的2种链接方法的DLL——静态链接到MFC的DLL和动态链接到MFC的DLL，指出了不同状态时所出现的问题以及解决办法。并以对话框资源为例来阐释。     

A portable digital DLL for high-speed CMOS interface circuits

A digital delay-locked loop (DLL) that achieves infinite phase range and 40-ps worst case phase resolution at 400 MHz was developed in a 3.3-V, 0.4-μm standard CMOS process. The DLL uses dual delay lines with an end-of-cycle detector, phase blenders, and duty cycle correcting multiplexers. This more easily process portable DLL achieves jitter performance comparable to a more complex analog DLL when placed into identical high-speed interface circuits fabricated on the same test-chip die. At 400 MHz, the digital DLL provides <250 ps peak-to-peak long-term jitter at 3.3 V and operates down to 1.7 V, where it dissipates 60 mW. The DLL occupies 0.96 mm²     

LabVIEW中DLL文件的创建及其应用

介绍了动态链接库文件的特点。以LabVIEW和Microsoft Visual C 为编程工具，详细介绍了DLL文件的创建过程。提供了开发自动测量系统时调用DLL文件编写子函数的例子，并给出了编程结果。本文提供的程序创建方法可推广应用于其他DLL文件的开发。     

GPS接收机码/载波跟踪环技术及其抗干扰能力分析

为了提高GPS接收机的抗干扰能力，美国采取了一系列抗干扰技术措施，其中码／载波跟踪环技术是现代数字GPS接收机普遍采用的技术。本文主要通过分析数字GPS接收机的码／载波跟踪环技术，根据经验法则确定的载波跟踪环（PLL）与码跟踪延迟锁相环（DLL）门限，对采用码／载波跟踪环技术的GPS接收机的抗干扰能力进行分析。     

延迟锁定环(DLL)及其应用

DLL可以产生精确的延迟效果而不受环境和工艺条件的影响 ,因而常用来生成稳定的延迟或多相位的时钟信号。文中介绍了延迟锁相环的结构 ,设计了 CMOS工艺 DLL具体电路 ,着重分析了新型的伪差分结构延迟单元 ,它可使设计简单而且单位延迟时间的选择更加灵活。文中还对 DLL在高速以太网发送电路中的应用作了具体的设计和仿真 ,运用 DLL使发送数据的上升、下降时间精确地控制在 4ns± 1 ns的范围内     

Convergence characteristic of delay-lock loop in multipathenvironment

The delay-lock loop (DLL) is utilised to recover the synchronising signal of the PN code in CDMA systems. However, few papers wholly illustrate the convergence characteristics of the DLL in multipath cases; this problem is studied by the authors. Theoretical analysis and simulation show that the DLL would lock at a point that is the linear combination of the different delays of each multipath signal, weighted by its power level. Therefore, there is an inherent error in the DLL in multipath environments     

一种用于DS-CDMA基站的全数字非相干延迟锁相环

本文根据直接序列扩频码分多址(DS-CDMA)系统上行链路伪随机码跟踪的特点,给出并分析一种全数字非相干延迟锁相环 (DLL),该DLL采用了二元鉴相和数字序贯滤波的实现结构。文中推导了多用户环境下环路的数学模型及鉴相误差统计特性,给出了跟踪性能的计算机仿真结果。研究结果表明,本文给出的DLL能以小的复杂度实现良好的跟踪性能,具有较高的应用价值。     

Analysis of DLL Jitter due to Voltage-Controlled Delay Line

In this paper we analyze jitter in a delay-locked loop (DLL) due to uncertainties in the voltage-controlled delay line (VCDL). To obtain a closed-form equation for jitter in the DLL, time-domain equations of the DLL are used. The jitter at the intermediate stages of the VCDL and the jitter of a conventional delay cell are analyzed. The simulation results show that the jitter of the DLL due to mismatch of the delay cells is zero at the beginning and end of the VCDL and is highest at the middle of the VCDL. Also, a DLL is designed in TSMC 0.18 μm CMOS technology to show the accuracy of the proposed analytical method.     

Design of tracking loop with dirty templates for UWB communication systems

Maintaining satisfactory synchronization between transmitter and receiver is one of the major challenges in carrying out highly efficient ultra-wideband (UWB) communications. For tracking purposes, the delay-locked loop (DLL) concept is applied. The DLL could be considered as a fundamental tracking technique for UWB devices. In this paper, the reference signal is generated at the receiver based on an approach called timing with dirty template. This approach promises to improve tracking performance while reducing receiver structure complexity. After the reference template is generated, we derive first-order and second-order DLL designs for UWB systems. Furthermore, we utilize the benefits of time-hopping codes to enhance noise handling ability of the DLL. Finally, the parameters of the proposed DLL will be selected to optimize tracking behavior in the presence of the ambient noise and Doppler effects. Simulation results show tracking performance across various DLL parameter values.     

Low-jitter multi-phase digital DLL with closest edge selection scheme for DDR memory interface

A multi-phase digital delay-locked loop (DLL) capable of a low-jitter feature for DDR memory interface is reported. The DLL repeatedly selects the output clock edge which is closest to the reference clock edge to reduce the total jitter. A test chip was fabricated in a 0.18 mm CMOS process to verify its functionality. The measured RMS and peak-to-peak jitter of the DLL are 6.2 and 20.4 ps, respectively. The power consumption of the DLL is 12 mW from a 1.8 V supply voltage.