Yield loss mechanisms in MOS-gated power devices

Defects which cause yield loss in MOS-gated power devices are discussed. Design and fabrication of a test element group for analysis of gate to source shorts in MOS-gated power devices are described. Experimental results obtained from these test elements are presented, based upon which it is demonstrated that gate to source shorts in power MOS-gated devices occur mainly along the edge of the polysilicon gate. The contact window opening step has been found to have a strong influence on the density of gate to source shorts     

A 1-V, 10-MHz, 3.5-mW, 1-Mb MTCMOS SRAM: with charge-recyclinginput/output buffers

This paper presents a high-speed and low-power SRAM for portable equipment, which is operated by a single battery cell of around 1 V. Its memory cells are made up of high-threshold-voltage (high-V_th) MOSFETs in order to suppress the power dissipation due to large subthreshold leakage currents. For designing peripheral circuitry, we use SRAM's special feature that input signals of each logic gate during the standby time can be predicted. Low-V_th MOSFETs are assigned for the critical paths of memory-cell access. The leakage current in each logic gate is reduced by high-V_th MOSFETs, which are cut off during standby. The high-V_th, MOSFET in one logic gate can be shared with another logic gate in order to enlarge effective channel width. To shorten the readout time, a step-down boosted-wordline scheme suitable for current-sense readout and a new half-swing bidirectional double-rail bus are used. The data-writing time is halved by means of a pulse-reset wordline architecture. To reduce the power dissipation, a 32-divided memory array structure is employed with a new redundant address-decoding scheme. Also, data transition detectors and a charge-recycling technique are employed for reducing the power dissipation of data-I/O buffers. A 64-K-words×16-bits SRAM test chip, which was fabricated with a 0.5-μm multithreshold voltage CMOS (MTCMOS) process, has demonstrated a 75-ns address access time at a 1-V power supply. The power dissipation during standby is 1.2 μW, and that at a 10-MHz read operation with the modified checkerboard test pattern is 3.9 mW for 30-pF loads     

谐振隧穿晶体管数字单片集成电路

阐述了谐振隧穿器件构成的与非门、单/双稳逻辑转换电路、或非门、流水线逻辑门、D触发器、静态存储器、多值逻辑和静态分频器等数字单片集成电路,它们具有高频高速、低功耗、多值逻辑、节点少、节省器件、简化电路等显著优势,将是数字集成电路后续小型化最有希望的代表。指出材料生长和芯片工艺制作等问题是其实现工业化生产的瓶颈。综述了国内外在该领域的研究现状和发展趋势,特别是美国已经有高水平的谐振隧穿晶体管数字单片电路问世,我国正在开展少量的研究工作。     

一种测试SRAM失效的新型March算法

随着工艺偏差的日益增加,新的失效机制也在亚100 nm工艺的CMOS电路里出现了,特别是SRAM单元。SRAM单元的故障由晶体管阈值电压Vt差异引起,而Vt差异又是由工艺偏差造成的。对于这类SRAM失效机制,需要把它映射成逻辑故障模型,并为检测出这类故障研究出新的March测试序列。针对这些逻辑故障模型,提出了一种新型的March算法序列;并通过验证,得到了很高的测试覆盖率。     

Automatic Test Generation for Combinational Threshold Logic Networks

We propose an automatic test pattern generation (ATPG) framework for combinational threshold networks. The motivation behind this work lies in the fact that many emerging nanotechnologies, such as resonant tunneling diodes (RTDs), single electron transistor (SET), and quantum cellular automata (QCA), implement threshold logic. Consequently, there is a need to develop an ATPG methodology for this type of logic. We have built the first automatic test pattern generator and fault simulator for threshold logic which has been integrated on top of an existing computer-aided design (CAD) tool. These exploit new fault collapsing techniques we have developed for threshold networks. We perform fault modeling, backed by HSPICE simulations, to show that many cuts and shorts in RTD-based threshold gates are equivalent to stuck-at faults at the inputs and output of the gate. Experimental results with the MCNC benchmarks indicate that test vectors were found for all testable stuck-at faults in their threshold network implementations.     

A detailed analysis and electrical modeling of gate oxide shorts in MOS transistors

The characteristics of devices with gate oxide short defects are investigated for both n-MOS and p-MOS transistors. Experimental results obtained from real and design induced gate oxide shorts are presented analyzing the defect-induced conduction mechanisms that determine the transistor behavior. It is shown that three variables (defect location, transistor type and gate polysilicon doping type) influence the characteristics of a defective device. Of interest is the prediction and observation of a particular gate oxide short type that can cause latchup. An electrical model is proposed and compared with experimental data. Such a model is developed to be used in electrical CAD environments without introducing a penalty in the simulation time.This work is supported by the Ministry of Education of Spain (CICYT TIC 046/95).     

Behavior of a radiation-immune CMOS logic family under resistiveshorts

Previous researchers had developed a special family of CMOS logic circuits which uses additional feedback transistors to provide immunity to radiation-induced errors for space-borne electronics. It was originally speculated that these transistors, representing a form of redundancy, might provide additional benefits, such as greater tolerance of manufacturing defects. Instead, the authors work shows that the redundant transistors, because of the way in which they are used, increase the sensitivity of the circuitry to manufacturing defects which manifest themselves as resistive transistor shorts, such faults cause: (1) logic errors at the affected gate output; and (2) an increase in the signal transition delay. Furthermore, these transistors lead to higher levels of quiescent supply current, making the circuits more difficult to test using quiescent current (I_DDQ) testing     

Development of the Self-Aligned Titanium Silicide Process for VLSI Applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Omega/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-/spl mu/m gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, Iinewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

Dynamic behavior of resistive faults in nanometer technology

Modeling the dynamic behavior for resistive shorts and opens at switch-level dictates the characterization of enhanced delay due to these faults with respect to the input combinations, fault sites, defect resistance and technology variation. The resistive fault model is applied to CMOS technologies with feature sizes of 350 nm, 180 nm, 90 nm, 45 nm and 32 nm, respectively. This model is targeted to transistor-level CMOS circuits. A static defect in a circuit (shorts or opens) is replaced by a resistor and a simple electrical analysis of the circuit is performed to obtain the timing variations which occurred during propagation of a logic value from gate inputs to gate output.     

Development of the self-aligned titanium silicide process for VLSI applications

A manufacturable self-aligned titanium silicide process which simultaneously silicides both polysilicon gates and junctions has been developed for VLSI applications. The process produces silicided gates and junctions with sheet resistances of 1.0-2.0 Ω/square. This paper describes the application of the self-aligned titanium silicide process to NMOS VLSI circuits of the 64K SRAM class with 1-µm gate lengths. Comparison of circuit yield data and test structure parameters from devices fabricated with and without the silicidation process has demonstrated that the self-aligned silicide process is compatible with both VLSI NMOS and CMOS technologies. The self-aligned titanium silicide process has some very significant manufacturing advantages over the more conventional deposited silicide on polysilicon technologies. In particular, the problems associated with etching and depositing a polycide gate stack are eliminated with the self-aligned process since the polycide etch is replaced with a much more straightforward polysilicon only etch. As gate lengths, gate oxide thicknesses, and source-drain junction depths are scaled, linewidth control, etch selectivity to the underlying gate oxide, and cross-sectional profile control become more critical. The stringent etch requirements are more easily satisfied with the self-aligned silicide process.     

90nm CMOS工艺SRAM的优化及应用

提出了一种优化的SRAM,它的功耗较低而且能够自我修复.为了提高每个晶圆上的SRAM成品率,给SRAM增加冗余逻辑和E-FUSE box从而构成SR SRAM.为了降低功耗,将电源开启/关闭状态及隔离逻辑引入SR SRAM从而构成LPSR SRAM.将优化的LPSR SRAM64K×32应用到SoC中,并对LPSR SRAM64K×32的测试方法进行了讨论.该SoC经90nm CMOS工艺成功流片,芯片面积为5.6mm×5.6mm,功耗为1997mW.测试结果表明:LPSR SRAM64K×32功耗降低了17.301%,每个晶圆上的LPSRSRAM64K×32成晶率提高了13.255%.     

Characteristics and reliability of the SEPROM cell

A new EPROM named SEPROM, based on a modified SEPOX process, is proposed and evaluated. The SEPROM offers a process compatibility to logic LSI's with higher packing density, since the area of the second gate oxide is equal to that of the first gate oxide. To improve the coupling capacitance ratio, which relates to write and read operations, a thin second gate oxide is required for the SEPROM cell at a risk of degradation in charge retention characteristics. A measured test device, however, shows sufficiently good characteristics both in programming and charge retention, due to the desirable structure of the cell. The SEPROM structure appears to be practical and promising for both EPROM and logic device applications.     

A 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro

We have used a 5-metal 0.18-μm CMOS logic process to develop a 16-Mb 400-MHz loadless CMOS four-transistor SRAM macro. The macro contains: (1) end-point dual-pulse drivers for accurate timing control; (2) a wordline-voltage-level compensation circuit for stable data retention; and (3) an all-adjoining twisted bitline scheme for reduced bitline coupling capacitance. The macro is capable of 400-MHz high-speed access at 1.8-V supply voltage and is 66% the size of a conventional six-transistor SRAM macro. We have also developed a higher-performance 500-MHz loadless four-transistor SRAM macro in a CMOS process using 0.13-μm gate length     

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations

With increasing inter-die and intra-die parameter variations in sub-100-nm process technologies, new failure mechanisms are emerging in CMOS circuits. These failures lead to reduction in reliability of circuits, especially the area-constrained SRAM cells. In this paper, we have analyzed the emerging failure mechanisms in SRAM caches due to transistor V/sub t/ variations, which results from process variations. Also we have proposed solutions to detect those failures efficiently. In particular, in this work, SRAM failure mechanisms under transistor V/sub t/ variations are mapped to logic fault models. March test sequences have been optimized to address the emerging failure mechanisms with minimal overhead on test time. Moreover, we have proposed a design for test circuit to complement the March test sequence for at-speed testing of SRAMs. The proposed technique, referred as double sensing, can be used to test the stability of SRAM cells during read operations. Using the proposed March test sequence along with the double sensing technique, a test time reduction of 29% is achieved, compared to the existing test techniques with the same fault coverage. We have also demonstrated that double sensing can be used during SRAM normal operation for online detection and correction of any number of random read faults.     

A multibit test trigger circuit for megabit SRAMs

A multibit test (MBT) trigger circuit for megabit SRAM packages with no unused pins is discussed. The features of the MBT trigger circuit are a logic trigger mode without using any additional pins and practical use of counter circuits. The essence of trigger mode selection is that two pulses are for MBT set and three pulses are for MBT reset. In this way, a logic trigger mode that does not use NC pins is especially effective as a 4-Mb SRAM. In addition, the proposed scheme is able to act as a logic trigger for an MBT circuit. The scheme is simple and effective. The logic trigger mode is proposed for future standardization     

Thickness limitations of SiO2 gate dielectrics for MOSULSI

The impact of gate leakage current on MOSFET performance is examined and limits on gate oxide thickness for static and dynamic logic are determined. Leakage current has been found to be a greater problem for static logic than for dynamic logic circuits. Gate leakage current limits the minimum oxide thickness to approximately 2 nm for static logic configurations, and to approximately 3 nm in dynamic logic circuits. A poor drain design can become a limiting factor for dynamic logic circuits and raise the minimum oxide thickness required. Switching delay of static logic is relatively immune to the effects of leakage current. A MISFET with a 2.6 nm thick gate insulator of Si₃N ₄ has been fabricated showing typical drain current characteristics, but with a large amount of gate leakage current     

Emitter function logic-logic family for LSI

A highly efficient large-scale integration logic family combining the advantages of multiemitter structures with the performance of emitter-coupled logic is discussed. Simplified gate structure has been found to reduce propagation delay, power and number of logic levels required for logic function realization. Conventional processing affords 2-5-pJ performance. The principle of operation of a basic AND-OR gate is shown and compared with the well known ECL gate. Fundamental gating and sequential logic functions are compared with the conventional inverting designs. The solid-state realization of a test gate is described. The speed-power performance advantage of emitter function logic gates and functions are contrasted with those of presently popular logic families.     

GaAs MOSFET High-Speed Logic

Enhancement-mode GaAs MOSFET integrated logic shows superior potential for applications in low-power high-speed integrated circuits. The speed / power performance of this logic was investigated by using GaAs MOSFET ring oscillators, fabricated using a low-temperature plasma oxidation technique for gate insulation. With an enhancement-depletion (E/D)-type ring oscillator, a minimum propagation delay of 110 ps per gate is obtained, with a power/speed product of 2.0 pJ. With an enhancement-enhancement (E/E) type, a minimum power/speed product of 26 fJ is obtained, with a 385-ps delay. These performances are equal to or better than those of GaAs MESFET logic, after adjustments are made for gate size. With further refinements in device geometry and improvements in gate oxide, GaAs MOSFET logic will be of great use in high-speed very-large-scale integrated circuits.     

A novel PMOS SOI polysilicon transistor

An advanced silicon-on-insulator (SOI) PMOS polysilicon transistor, featuring an inverted gate electrode and self-aligned source/drain and gate/channel regions, is developed and characterized. Selective oxidation is used to form self-aligned thin polysilicon channel regions with thicker source/drain polysilicon regions. The gate electrode is formed by a high-energy boron implant into the underlying silicon substrate. Since the gate oxide is formed over single-crystal silicon rather than polysilicon, an improvement in gate oxide integrity is possible. The resulting SOI PMOS device is suitable for high-density static random access memory (SRAM) circuit applications and exhibits excellent short-channel behavior with an on/off current ratio exceeding six orders of magnitude     

一种基于全数字锁相环的SRAM实速测试方案

提出了一种采用实速测试方式测试SRAM性能参数及可靠性的方案。该方案在内建自测试(BIST)电路的基础上,通过增加一个超高速ADPLL为SRAM性能的实速测试提供一个高频时钟,同时还加入延时链来产生不同相位的4个时钟。通过调整这4个时钟的相位来获得SRAM的关键性能参数,如存取时间、地址建立和保持时间等。该方案在UMC 55nm CMOS标准逻辑工艺下流片验证。测试结果显示,SRAM最大测试工作频率约为1.3GHz,测试精度为35ps。