Impact of Substrate Digital Noise Coupling on the High-Frequency Noise Performance of RF MOSFETs

The impact of digital noise coupling through the substrate on RF MOSFETs was investigated in terms of the noise figure (NF) of the device up to 26.5 GHz. Previous works on the substrate digital noise coupling have treated the effect mostly in terms of the electrical isolation between ports, rather than actual devices, which does not provide direct information on the degradation of actual device performance parameters from such coupling. In this work, an actual NMOSFET was employed for test and the effect was described in terms of NF, a practical device performance parameter. The results show that NF is significantly degraded as the device enters the weak inversion state and/or $V_{rm ds}$ becomes smaller, suggesting a trade-off between low power operation and immunity against the substrate noise coupling. Also, it is experimentally verified that devices with a dual guard ring showed much smaller NF than those with a single guard ring.      

数字粉红噪声生成研究

介绍了利用DSP方法和Voss算法生成数字粉红噪声的原理,并对生成的粉红噪声性能参数进行了比较和评价,推荐了各种方法的应用场合。     

Substrate Noise Coupling in SoC Design: Modeling, Avoidance, and Validation

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed     

Modeling, design and characterization of a new low-jitter analog dual tuning LC-VCO PLL architecture

This paper describes the modeling, design, and characterization of a low-jitter 2.4-GHz LC-VCO PLL architecture realized in a standard 0.12-/spl mu/m CMOS technology. It features an analog dual control loop for fine and coarse VCO tuning that allows very low VCO gain (60 MHz/V) for noise rejection while maintaining a wide tuning range. The coarse input of the VCO is driven by an analog circuit that adjusts the VCO gain in a continuous manner. Measurements demonstrate an integrated jitter of 0.74 ps that is 43% lower compared to results from a standard PLL topology (STD PLL) with a single control loop. The PLLs have the same bandwidth and output frequency range and were built on the same wafer for comparison. The circuit area of the proposed LC-VCO PLL is 0.7 mm/sup 2/ and the power consumption is 32 mW. The area and power consumption of the proposed LC-VCO PLL are less than 1% larger compared to the STD PLL.     

一种LC-VCO 1/f3相位噪声优化方法

建立了差分互补型电感电容压控振荡器(LC-VCO)的等效分析模型.采用有效截止频率厂T.e.来表征MOS管的充放电能力,结合振荡器起振后共模输出电压下降的现象,提出了优化1/f3相位噪声的方法.采用该方法并结合跨导效率gm/ID设计方法,实现了LC-VCO 1/f3相位噪声的优化,并在0.18 μm CMOS工艺上获得验证.结果表明,该优化方法可以使频偏在1 kHz以内的相位噪声改善2～3 dB,可用于开环LC-VCO作为本振的低功耗无线收发机及高性能晶体振荡器的电路设计中.     

Comprehensive Electromagnetic Modeling of On-Chip Switching Noise Generation and Coupling

A comprehensive modeling methodology is presented for the investigation of on-chip noise generation and coupling due to power switching. The backbone of the methodology is an electromagnetic model for the on-chip portion of the power grid. This allows for the impact of the displacement current density and, hence, electromagnetic retardation, to be taken into account in the accurate modeling of the power grid behavior at picosecond switching speeds. In this manner, and through the interfacing of this model with an electromagnetic model for the package portion of the power grid, which is described in terms of a multiport rational matrix transfer function, the impact of package-chip electrical interactions on switching noise can be modeled with electromagnetic accuracy. The electromagnetic model for the power grid is complemented by a resistance-capacitance model for the semiconductor substrate, which is capable of modeling local substrate induced noise coupling between neighboring circuits. Finally, distributed resistance, inductance, capacitance and conductance circuits for signal wires are extracted and used to provide for a transmission line-based modeling of crosstalk and power grid induced signal degradation. Transient simulations using the proposed comprehensive model are carried out using a hybrid time-domain integration scheme which combines a SPICE-like engine for the analysis of all circuit netlists and the nonlinear drivers incorporated in the model with a numerical integration algorithm suitable for the expedient update of the state variables in the discrete electromagnetic model for the power grid.      

Design and realization of an ultra-low-power low-phase-noise CMOS LC-VCO

A fully integrated cross-coupled LC tank voltage-controlled oscillator(LC-VCO) using transformer feedback is proposed to achieve a low phase noise and ultra-low-power design even at a supply below the threshold voltage. The ultra-low-power VCO is implemented in the mixed-signal and RF 1P6M 0.18-μm CMOS technology of SMIC. The measured phase noise is-125.3 dBc/Hz at an offset frequency of 1 MHz from a carrier of 2.433 GHz,while the VCO core circuit draws only 640μW from a 0.4-V supply.The designed VCO can...     

Plasma-Induced Defect-Site Generation in Si Substrate and Its Impact on Performance Degradation in Scaled MOSFETs

Plasma-induced ion-bombardment damage was studied in terms of defect sites created underneath the exposed Si surface. From the shift of capacitance–voltage ($C$– $V$) curves, the defect sites were found to capture carriers (being negatively charged in the case of an Ar plasma exposure). This results in a change of the effective impurity-doping density and the profile. We also report that the defect density depends on the energy of ions from plasma. A simplified and quantitative model is proposed for the drain–current degradation induced by the series-resistance increase by the damage. The relationship derived between the defect density and the drain–current degradation is verified by device simulations. The proposed model is useful to predict the device performance change from plasma process parameters.      

A low-phase-noise LC-VCO with an enhanced-Q varactor for use in a high-sensitivity GNSS receiver

An LC-VCO with an enhanced quality factor(Q) varactor for use in a high-sensitivity GNSS receiver is presented.An enhanced A-MOS varactor is composed of two accumulation-mode MOS(A-MOS) varactors and two bias voltages,which show the improved Q and linearization capacitance-voltage(C-V) curve.The VCO gain(K_(vco)) is compensated by a digital switched varactors array(DSVA) over entire sub-bands.Based on the characteristics of an A-MOS,the varactor in a DSVA is a high Q fixed capacitor as it is switched off,and a moderate Q tuning varactor when it is switched on,which keeps the maximal Q for the LC-tank.The proposed circuit is fabricated in a 0.18μm 1P6M CMOS process.The measured phase noise is better than -122 dBc/Hz at a 1 MHz offset while the measured tuning range is 58.2%and the variation of K_(VCO) is close to±21%over the whole of the sub-bands and the effective range of the control voltage.The proposed VCO dissipates less than 5.4 mW over the whole operating range from a 1.8 V supply.     

Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid

In this paper, an analytical model for the current draw of an on-chip bus is presented. The model is combined with an on-chip power supply grid model in order to analyze noise caused by switching buses in a power supply grid. The bus is modeled as distributed resistance–inductance–capacitance (RLC) lines that are capacitively and inductively coupled to each other. Different switching patterns and driver skewing times are also included in the model. The power supply grid is modeled as a network of RLC segments. The model is verified by comparing it to HSPICE. The error was below 8%. The model is applied to determine the influence of driver skewing times on maximum power supply noise.      

基于FPGA的全数字FSK调制解调器设计

根据数字信号FSK调制和解调的工作原理,采用层次化、模块化方法设计了一种基于FPGA芯片的FSK调制解调器;用数字键控法实现了调制,用过零检测法实现了全数字解调。同时结合系统功能实现的需要,设计了伪随机序列(m序列)模块。整个设计基于ALTERA公司的QuartusⅡ开发平台,并用Cyclone系列FPGA实现。所设计的调制解调器具有体积小、功耗低、集成度高、软件可移植性强、扰干扰能力强的特点,符合未来通信技术设计的方向。     

全数字PSK调制解调器结构的研究

提出了一种全数字PSK调制解调器的结构模型.在此基础上,采用SystemView5.0软件进行了QPSK调制的仿真实验,验证了其合理性,对工程实践具有较大的参考价值.     

基于软件无线电的FSK系统设计

文中设计了一种基于软件无线电思想的数字FSK调制解调器系统。在掌握和分析诸多调制解调器的设计原理和方法之后,通过设置波形发生器,存储调制的正弦波,用这种较简单的方法实现了调制。并运用软件无线电的方法,提出了一种基于DFT原理的经典谱估计法,用以实现2FSK信号的解调方案,并在FPGA中设计实现。经验证方法可行。     

Utilizing System Dynamics Modeling to Examine Impact of Deregulation on Generation Capacity Growth

Widespread deregulation of the U.S. wholesale power industry in the late 1990s was followed in many regions by substantial overbuilding of capacity. This behavior calls in to question the longer term stability of the deregulated industry. A dynamic model structure of power-producing regions, suitable for longer term analysis of capacity investment and market stability, was created and validated against 20 years of data for two regions. Monte Carlo simulations suggest that for a realistic range of assumptions, the deregulated wholesale power markets are substantially more cyclical than they would have been under a regulated monopoly regime. The models can be improved in several areas, most notably further simplification, analysis of impacts of market structure and design, and addition of transmission constraints among regions.     

A Model for Assessing the Impact of an Impulsive Noise Process on Land-Mobile Communication

This paper develops a statistical model with which the impact of a given noise random process upon a land-mobile communication system (LMCS) can be assessed. This model is useful for computing an upper bound for the fraction of communication-system messages which are affected by any given EMI at any given interference level. Applications of the model include, for example, bounding the interference effects on land-mobile communication of the EMI produced by arbitrary electrical apparatus.     

一种宽带数字噪声产生系统的实现

采用常规VCO产生调频射频噪声，尽管具有射频带宽宽、设备简单的优点，但存在瞄准精度低、带内平坦度差的缺点，而采用数字式噪声的方案则具有瞄准精度高、带内平坦度好、统计特性好的特点。文中介绍了一种基于数字技术的噪声产生系统，能够产生宽带干扰噪声、梳状波干扰噪声和频率凹波干扰噪声三种噪声形式。     

Phase Noise and Transient Times for a Binary Quantized Digital Phase-Locked Loop in White Gaussian Noise

Digital phase-locked loops of the type employing discrete phase adjustments form an interesting class for which both steady-state and transient performance may be determined in the presence of additive white Gaussian noise. A general technique for obtaining this analysis is presented. A class of "sequential filters" is described that appears to be well suited to this type of loop. Their performance is characterized by a variable number of inputs per output (depending upon the input sequence) and the use of coarse quantization. Two specific examples are discussed. The closed-loop transient analysis shows these loops to have effectively a slew-rate limited phase adjustment, indicating that they are decidedly nonlinear. A digital loop "quasi-bandwidth" measure is defined in terms of this transient response. This definition allows the comparison of digital loops on a basis of equal signal-to-noise ratios within the loop bandwidth and, to a limited extent, makes possible a similar comparison of the digital loops with linear loops. Performance of the digital loops is found to be similar to that of the first-order linear phase-locked loop model for low loop bandwidth signal-to-noise ratio but reaches a limiting minimum phase error due to quantization of the phase adjustments for high signal-to-noise ratio. This limit, however, can be set as low as desired by choosing a small enough phase-correction quantum. The digitalloop bandwidth is found to vary with the signal energy per noise spectral density ratio rather than with the signal amplitude as in the case of the linear analog model.     

Identification of Dominant Noise Source and Parameter Sensitivity for Substrate Coupling

A simple, yet physically intuitive macrolevel model is presented to identify the dominant substrate coupling mechanism at the early stages of the design process, while simultaneously considering multiple parameters. Furthermore, the sensitivity of substrate noise to these parameters is evaluated, demonstrating the nonmonotonic dependence of noise on rise time. The design implications of the proposed analysis are discussed, identifying the preferred noise reduction technique for a specific set of operating points.     

Cable Modem的原理与反向噪声的控制

介绍Cable Modem的基本概念、传输方式、标准规范，并对影响Cable Modem工作稳定性的反向噪声问题进行技术分析，并提出预防控制措施。