A study on GTO turn-off failure mechanism—A time- and temperature-dependent 1-D model analysis

A 1-D model is presented for use in analyzing the GTO thyristor turn-off process, including the conduction region squeezing effects as well as the current due to temperature variation, i.e., thermal diffusion and the current due to bandgap variation with temperature change. The model simulates current-voltage characteristics for the current concentrated area, where the current density increases almost linearly with the anode voltage. It is found that the nonuniformity in the p-base sheet resistance is a significant cause for the current concentration because of the enhanceddv/dtcurrent due to the excess carrier removal from the highly injected n-base. The model also predicts the limitation to the anode voltage imposed on the device before the current is completely turned off.     

Current distributions at the lateral spreading of electron-hole plasma in a thyristor

By using the potential probe method, the turn-on action of the three junctions of a thyristor associated with the plasma spreading was investigated as a function of the anode current density Ja. By increasing Ja, the width of the transient region between the ON and the OFF region was increased in the p-base layer but decreased in the n-base layer. The build up of the excess carriers in the p-base layer was due to the lateral field in the transient region, while in the n-base layer it was mainly due to the lateral diffusion from the ON region.     

Suppressing latchup in insulated gate transistors

Two-dimensional computer modeling of insulated gate transistor (IGT) structures has been used to demonstrate the suppression of latchup in the parasitic thyristor by increasing the p-base conductivity using a deep p+ diffusion in the device cells. Experimental verification of these modeling results has been performed with thyristor latching current density of over 1000 A per cm²achieved in 600-V devices at room temperature.     

Theoretical and experimental characteristics of the base resistancecontrolled thyristor (BRT)

Described are the characteristics of a new MOS gated thyristor structure called the base resistance controlled thyristor (BRT), in which the turn-off of a thyristor built with an N drift region is achieved by reducing the resistance of the p-base region under MOS gate control. A p-channel MOSFET used to achieve turn-off is formed in the N drift region. The device is designed so that, when the p-channel MOSFET is switched on, holes are diverted from the p-base region of the thyristor into the adjacent p⁺ region, raising the holding current of the thyristor above the operating current level, and turning off the thyristor. Results of extensive 2-D numerical simulations that have been performed to demonstrate operation of this new device concept are discussed. Experimental results on 600-V devices fabricated with an IGBT process have corroborated theoretical predictions. Current densities above 900 A/cm² have been turned off at room temperature with a gate bias of -10 V     

A time- and temperature-dependent 2-D simulation of the GTO thyristor turn-off process

GTO thyristor turn-off process is analyzed for a resistive load case by performing an exact two-dimensional time- and temperature-dependent numerical simulation. A newly defined concept "on-region" is introduced to help understanding of the simulation results. Excess carrier plasma (on-region) in the p-base is squeezed finally to as narrow as 60 µm wide, accompanying a large current density increase at the center of the middle junction. The carriers in the n-base are found not to be greatly affected by the initial plasma squeezing in the p-base. After the on-region width in the p-base reaches its final limit, the excess carriers around the middle junction of the final on-region is rapidly reduced, resulting in complete anode current turn-off.     

Gate turn-off capability of depletion-mode thyristors

Experimental results are described which demonstrate the ability to switch a thyristor from its ON state to its OFF state by using a depletion layer formed by the application of gate bias to a trench-gate MOSFET integrated within the thyristor structure. The maximum controllable current is found to be a function of the gate bias voltage, the trench depth, and the ambient temperature. The maximum controllable current can be increased by increasing the trench depth and decreasing the p-base sheet resistance. The maximum controllable current decreases at high temperatures, as in the case of other MOS-bipolar devices, but is significantly better than for previous devices. The absolute values of the maximum turnoff current are well above 1000 A/cm² at room temperature and 500 A/cm² at 200°C     

A fast CAD model of plasma spread in thyristors using aseminumerical time-domain approach

This paper presents a fast CAD model to calculate plasma-spreading velocity in large area thyristors. The model is based on the two-dimensional two-transistor circuit model of a thyristor. At first, a simplified numerical solution of the semiconductor equations is developed to obtain the current amplification factor and the base transit time of each transistor of the thyristor model as a function of the emitter current density. The turn-on recurrence relations governing the evolution of the anode current at different lateral points are then derived by the transit function method. The time constant of the anode current rise and the plasma spreading velocity are calculated as functions of the anode current density. The results of simulation are in close agreement with the corresponding measured values of plasma spreading velocity by the electrical probes method. This agreement confirms the validity of our model over a large scale of anode current densities     

Floating base thyristor

The floating base thyristor (FBT) is a new thyristor structure in which its p-base region, containing a p⁺ region is not shorted to the n⁺ emitter. Using the DMOS process, an n-channel and a p-channel MOSFET are integrated with the thyristor structure. The device operates in the thyristor mode with a low ON-state voltage drop at even high current densities when a positive bias is applied to, both gates. When a negative bias is applied to the OFF gate, the device operates in the IGBT mode with the saturated current controlled by the positive bias applied to the ON gate     

Investigation of the lateral turn-on process of thyristors with an epitaxial p-base

In this paper, the effect of the p-base doping concentration NAon the spreading velocity vsin power thyristors is examined. Chemical vapor deposition (CVD) techniques are used to produce the p-base layer, in order to change the p-base doping concentration and thickness independently. The results show a large reduction of vswith growing p-base doping concentration. At a doping concentration higher than 5 × 10¹⁶/cm³the spreading velocity follows a power law with an exponent of -0,9. The introduction of a sandwiched low-doped player between the p⁺-base and the n-emitter slows down the plasma propagation. The decrease of vs, in both cases, is attributed to the reduction of the current gain β2of the n-p-n transistor with doping concentration. In order to explain this behavior, a simple expression for the spreading velocity is derived, which relates the spreading velocity to the time constant of current rise trand consequently to the feedback loop gain (β1β2) of the two transistor components. In this derivation, only the lateral drift current in the p-base is taken into account. It was found that vsis given byv_{s} sim 1/t_{r} sim ln beta_{1}beta_{2}, in good agreement with the experiment.     

Light-triggering phenomena on thyristors with an n-emitter layer over the light-sensitive gate area

Turn-on phenomena of a light-activated thyristor are analyzed using a one-dimensional numerical model that consists of the full set of semiconductor device equations, including the optically generated current and the effect of the shorted emitter. Results indicate that the photocurrent Ipis induced by photovoltaic effects of then_{E}-p_{B}junction and that its flow is in the reverse direction of the anode current IA. Consequently, Ipcirculates through the p-base, the short path placed across then_{E}-p_{B}junction and the n-emitter resulting in a contribution to the light triggering, in addition to that of IAcaused by the conventionalP_{B}-n_{E}-p_{E}transistor action. In order to confirm the predicted behavior of the photocurrents, light-triggered 4-kV devices were fabricated. The experimental results thus obtained confirm the conclusions drawn from the model analysis.     

Observation of turn-on action in a gate-triggered thyristor using a new microwave technique

The turn-on action by the p-base and n-emitter gates in a thyristor was studied by a new microwave technique. The initial conducting area, the lateral distribution of gate current flowing through the junction, and the time variation of excess carrier density injected into the n-base by the gate current were determined by measuring the reflection of microwave energy, vertically incident upon a small area (0.2 × 0.2 mm²) of the n-emitter layer. The new microwave technique has proved to be useful in designing new gate structures and in studying the operation of new devices.     

A New Emitter Switched Thyristor (EST) employing Trench Segmented p-base

A new emitter switched thyristor (EST) employing trench segmented p-base, which successfully improves the forward I-V and switching characteristics with decreasing the device active area, is proposed and verified experimentally with using shallow trench process of novel junction termination extension (JTE) method. The latching current of EST is determined by the p-base resistance of upper npn transistor. Floating n+emitter of conventional EST is enlarged to obtain large base resistance. However, the proposed EST increases the p-base resistance with shorter floating n+ emitter than that of conventional one. Shallow trench in floating emitter region forms the highly resistive p-base region under the bottom of trench. The experimental results show that the shortened floating n+ emitter and lowered latching current of proposed EST decrease experimentally the forward voltage drop by 17.7% and snap-back phenomenon with small active area. The breakdown voltage of series lateral MOSFET of proposed EST is increased from 7 to 14 V due to the trench filled with oxide which results in vertical redistribution of electric field, therefore current saturation capability and forward biased safe operating area (FBSOA) of proposed EST are enhanced. The simulation results show that the switching operation is performed successfully at the blocking voltage of 600 V and Eoff of the proposed one is reduced by 3.7%. The measured inductive load switching characteristics also shows that Eoff of proposed one is improved by 7.2%.     

Simulated turn-off of 4H-SiC gate turn-off thyristors with gateelectrodes on the p-base or the n-base

Turn-off simulations of a 4H-SiC GTO thyristor structure having a gated p-base and p-type substrate are compared with that having a gated n-base and n-type substrate. Two gate drive circuits are considered, one with a voltage source and resistor between the gate and adjacent emitter region, and the other with a voltage source and resistor between the gate and farthest emitter region. The gated n-base thyristor's substrate current increases atypically before the device turns off. Also, the gated n-base structure turns off when the gate circuit is connected directly to the emitter region furthest from the gate region, but the gated p-base structure does not. Furthermore, turn-off gain is lower for the gated n-base structure due to mobility differences as demonstrated by current-voltage (I-V) and current versus time (I-t) curves     

CB-BRT: a new base resistance-controlled thyristor employing aself-aligned corrugated p-base

We propose and fabricate a new base resistance-controlled thyristor (BKT) employing a self-aligned corrugated p-base. The new device, entitled CB-BRT, suppresses the snap-back effectively and increases the maximum controllable current. Experimental results show that the snap-back of the CB-BRT is reduced significantly when compared with that of the conventional BRT. Also, the maximum controllable current of the CB-BRT increases as compared with the conventional BRT     

Controlled turn-on thyristors

In a one or more amplified stage thyristor design it is possible to control the peak current level of all but the final stage with impedance built into the p-base zone. This impedance reduces both the current and the duty cycle of the protected amplifying stage effectively protecting it from undesirable temperature rises during turn-on. A further bonus and perhaps equally important is the fact that the amplifying stage and its current control impedance can be used to reduce and essentially fix the voltage level at which the following stage turns on. This results in a lower voltage, lower stress turn-on of the following stage, and a device essentially protected from di/dt turn-on failure. This paper describes several aspects of controlled turn-on in the context of a 2.6- and 6-kV light triggered thyristor. In particular we discuss selection of the resistor value, the problem of unwanted current control resistor modulation by device current as well as some factors affecting the proper wattage of such resistors. We also discuss the role current control resistors can play in controlling avalanche current from known locations on the device.     

A new buried-gate GTO structure having a large safe operating area

A novel structure of a buried-gate GTO (gate turn-off thyristor) was proposed for expanding the safe operating area (SOA) of unit-GTOs. The SOA of unit-GTOs in a test sample GTO and the spike voltage at the limit of turn-off of the test sample were investigated experimentally. The SOA was calculated by means of a simple model in order to study the mechanism of the expansion of SOA in the structure. The SOA was expanded due to the reduction of the sheet resistance of the p-base layer by the fine mesh pattern of the buried layer. Corresponding to the increased size of the SOA, the spike voltage increased to 1000 V     

2500-V 600-a gate turn-off thyristor (GTO)

GTO self-turn-off capability provides an advantage over an ordinary thyistor, because of forced commutation circuit removal upon inverter and chopper application, thus substantially reducing equipment size, weight, and mechanical noise. A series of high-power GTO's has been developed, with the present 2500-V-600-A unit as its peak. The most essential design problem for this unit is to establish a principle for increasing maximum gate turn-off current (IATO), while keeping overall thyristor characteristics in reasonable balance. High IATOwas attained by decreasing p-base sheet resistance, as well as decreasing n-emitter finger width. Excellent thyristor characteristics were obtained by adopting a low acceptor concentration near the cathode-gate junction. From a device process point of view, introducing a phosphorus redeposition annealing increased carrier lifetime in the p base to a sufficiently high level. This process contributed most strikingly to improving the off-state voltage.     

Latchup criteria in insulated gate p-n-p-n structures

Latchup in insulated-gate p-n-p-n structures may be due either to the well-known thyristor action or to a regenerative feedback originating from substrate bias in the MOS gate. Simple models are presented to interpret and to predict both latching modes. It is shown that these two latching modes may occur consecutively as the current level rises, and that the device may, therefore, exhibit three distinct regions of forward operation. Experiments on special test devices in which the p-base region can be accessed externally support the theory well.     

A high-voltage light-activated thyristor with a novel over-voltageself-protection structure

A high-voltage self-protected thyristor with a well structure formed in its p-base layer whose operation is based on avalanche breakdown is described. The device structure is simple and easy to fabricate compared to other avalanche-type devices. Numerical analyses and experiments demonstrate that the breakover voltage can be controlled by varying the well diameter and/or its depth. The breakdown voltage fluctuation of the device is 10% when the junction temperature is varied from 23 to 100°C. The device is turned on safely at 7300 V     

Modeling of minority-carrier surface recombination velocity atlow-high junction of an n+-p-p+ silicon diode

Modeling of recombination velocity of minority carriers at the p-p ⁺ low-high junction end of the p-base region of n⁺-p-p⁺ silicon diodes is carried out by taking the minority-carrier recombination effects in the space-charge region (SCR) of the low-high (L-H) junction into account. Solving Poisson's equation in the SCR numerically revealed that the SCR is composed of an accumulation layer on the p side and a depletion layer on the p⁺ side. Generally, the depletion layer is very thin as compared with the accumulation layer, and the built-in potential across the depletion layer never exceeds the thermal voltage, i.e. kT/q. Further, the minority-carrier recombination in this layer is also insignificant. For most L-H junction-based silicon devices, in practice, the minority-carrier recombination in the accumulation layer controls the value of the effective minority-carrier recombination velocity (S_eff) at the back surface of the p-base region and the influence of the recombination in the heavily doped p⁺ region is less significant