共查询到19条相似文献,搜索用时 156 毫秒
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在对跨域BGP/MPLS VPN各种实现方案进行分析的基础上,结合大规模接入汇聚路由器的实际需求,提出了一种高速条件下的跨域BGP/MPLSVPN转发引擎结构,并针对该转发引擎的查表部分设计了一种基于双表融合的TCAM表项结构,对报文的操作类型进行了合理的设计,最后利用xilinx公司的virtex4 xc4v1x160 FPGA芯片对该转发引擎进行了实现,最终的测试结果表明该转发引擎能够有效的工作,达到了大规模接入汇聚路由器的性能需求. 相似文献
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高速转发引擎是高性能IPv6路由器的关键技术,文章设计了一种IPv6高速转发引擎的硬件结构,编写了硬件结构的VerilogHDL模型,进行了仿真和逻辑综合,并成功用XILINX的FGPA对转发引擎进行了验证。测试结果表明,该文设计的转发引擎的结构正确,可以达到2.5G端口线速转发,满足了设计要求。 相似文献
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互联网高速发展中的多种应用诉求,希望路由系统能提供一种工作模式可配置的转发引擎.然而,现有高性能分布式路由系统中线卡独享固定转发引擎的结构,限制了转发体系的灵活扩展.提出了转发引擎与线卡分离的新型路由器体系结构,形成共享的、可扩展的转发单元群.继而,设计了工作模式可配置的共享转发引擎FERM(Forwarding Engine with Reconfigurable Mode),并基于FERM提出了负载均衡、带宽约束和绿色节能等3种不同的转发工作模式.最后,给出了面向新型转发引擎的路由系统实现方法,并通过模拟实验分析验证了其优越性. 相似文献
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Internet的飞速发展要求将来的核心路由器具有超高速的转发能力,路由器设计的难点之一就是超高速转发引擎的设计,文章给出了一种超高速转发引擎的并行机制流水线设计方案,并给出了基于该思想的详细实现,测试结果表明依据该方案实现的转发引擎达到了10Gbps的转发处理能力。 相似文献
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在国家863重大课题"大规模接入汇聚路由器(ACR)"设计PIM-SM(Protocol Independent Muhicast-Sparse Mode)组播路由协议的分布式实现中,针对现有处理PIM-SM协议控制报文中的注册消息(Register message)的方法会引起路由器控制平面与数据处理平面交互信息量过大,并且消耗路由器处理负载最多的缺点,提出一种基于并行处理的高速转发方法,该方法便于直接在转发引擎以硬件实现,在不影响线速转发组播数据的前提下,无需将组播数据上报路由器主控平面,减少了两平面交互的数据量,缩短了组播报文在路由器内部的处理时间,能够达到更好的组播数据转发性能. 相似文献
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并行超流水IPv6转发处理技术研究 总被引:1,自引:0,他引:1
转发处理引擎是高性能IPv6路由器的设计难点之一。在研究了并行处理技术、流水线设计理论以及TCAM技术的基础上,该文提出了一种并行超流水的转发处理引擎,模拟试验测试显示,该引擎在满负荷工作的条件下,其包转发率、丢包率等多个方面比传统的转发处理引擎性能优越。 相似文献
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Trie树数据结构的实现方法灵活,所需存储器空间小,是实现高速路由查找和分组转发的理想选择。为满足10 Gb/s线速度网络处理器中微引擎的设计要求,提出一种基于最优平衡、多层存储的Trie树路由查找算法。建立一种平衡的压缩树结构,将该树中相邻的多层节点压缩到一个存储节点中。通过构造特定的数据存储结构来减小树的搜索深度,以空间换取时间,从而提高路由查找速度和分组转发效率。在网络处理器的查找微引擎设计中实现Trie路由查找算法,实验结果表明,单个微引擎的查找速度为4.4 Mb/s,能达到节省存储空间、提高查找效率的效果。 相似文献
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This paper deals with an in-line network security processor (NSP) design that implements the Internet Protocol Security (IPSec) protocol processing for the 10 Gbps Ethernet. The 10 Gbps high speed data transfer, the IPSec processing including the crypto-operation, the database query, and IPSec header processing are integrated in the design. The in-line NSP is implemented using 65 nm CMOS technology and the layout area is 2.5 mm×3 mm with 360 million gates. A configurable crossbar data transfer skeleton implementing an iSLIP scheduling algorithm is proposed, which enables simultaneous data transfer between the heterogeneous multiple cores. There are, in addition, a high speed input/output data buffering mechanism and design of high performance hardware structures for modules, wherein the transfer efficiency and the resource utilization are maximized and the IPSec protocol processing achieves 10 Gbps line speed. A high speed and low power hardware look-up method is proposed, which effectively reduces the area and power dissipation. The post simulation results demonstrate that the design gives a peak throughput for the Authentication Header (AH) transport mode of 10.06 Gbps with the average test packet length of 512 bytes under the clock rate of 250 MHz, and power dissipation less than 1 W is obtained. An FPGA prototype is constructed to verify the function of the design. A test bench is being set up for performance and function verification. 相似文献
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This paper presents the design and implementation of a protocol offload engine that processes TCP/IP and remote direct memory access (RDMA) protocols by means of hardware/software coprocessing. In the offload engine, time-consuming operations such as TCP/IP header generation are implemented as hardware to improve performance. The software performs control operations and RDMA header generation. In the experiments and analyses, it is proved that the hardware can provide satisfactory performance to process all operations at speeds of over 1 Gbps. Our engine can offload most protocol processing overheads – up to 95% to 100% – from the host CPU. Finally, although the embedded processors operate with a 300 MHz clock that is seven times slower than the clock of the host CPU, our engine shows maximum bandwidths of 673 Mbps for TCP/IP and 551 Mbps for RDMA on a gigabit Ethernet network. 相似文献
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CRC编码由于其简单的编码规则的在网络及存储等诸多场合得到广泛应用,随着现代存储和传输技术的发展,软件编码校验已难以满足Gbit级高速传输的需要。基于FPGA技术设计了一个采用多通道高度并行技术实现的高速循环冗余校验(CRC)系统。系统采用五个2Gbps校验通道并行工作的方式来达到10Gbps的数据吞吐率,系统实现采用VerilogHDL硬件描述语言设计,在QuartusII8.0平台上进行综合与布线,并将该处理单元封装为独立的IP核,并以Altera公司的EP2C20F484C6芯片为下载目标进行实现验证。综合结果表明,本设计可满足高速数据完整性检查的速率要求。 相似文献
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Data link level forwarding provides simple and fast packet forwarding capability. One primary reason for the simplicity of layer 2 forwarding comes from its short, fixed length labels. A node forwarding at network layer must parse a relatively large header, and perform a longest-prefix match to determine a forwarding path. When a node performs layer 2 forwarding, it can do direct index lookup into its forwarding table with the short header. It is arguably simpler to build layer 2 forwarding hardware that it is to build layer 3 forwarding hardware because the layer 2 forwarding function is less complex (Callon et al., 1997). By bypassing the conventional IP forwarding (the packet assembly/reassembly) process using cell-relaying, we could dramatically reduce both the IP packet processing delay and the queuing delay at the router (Esaki et al., 1997). The paper targets the problem of managing and reducing delays in IP over ATM communications that are associated with the implementation of IPv6 protocol. 相似文献
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6LoWPAN使得在无线传感网络上进行基于IPv6的数据传输成为可能, 它定义了route-over和mesh-under两种路由策略. 针对传统的route-over策略在分片转发中存在的问题, 提出了基于虚电路的route-over分片流水转发策略, 详细介绍了该改进策略的详细设计, 即根据第1个分片的IP压缩头部信息建立后续分片的转发映射. 仿真实验结果表明, 改进的策略较原始策略在网络传输和时延上有更好的表现. 相似文献
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针对当前基于ARM和DSP的嵌入式图像处理系统前端采集速度慢和图像处理算法不易加速的缺点,设计了一种基于HDMI接口的全高清(分辨率1920×1080)实时视频采集与图像处理系统;采用500万像素级别CMOS摄像头作为前端数据源,主芯片内部采用ARM+FPGA的异构架构,兼备FPGA的并行处理能力与ARM处理器任务调度功能;基于AXI协议设计了自定义数据存储传输的IP核,实现了处理速度与带宽最大化;利用HLS工具将图像预处理算法快速打包生成IP核,在FPGA中实现图像算法的硬件加速,完成图像处理系统平台原型机的设计;与传统的PC机和相机的机器视觉平台相比,该系统运行平均耗时在10 ms以内,实时检测效果令人满意,有效解决了低功耗与高数据带宽和处理速度之间的矛盾,为后端结果分析和边缘加速提供了良好支持。 相似文献
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基于FPGA的高速硬件防火墙报文检测系统设计 总被引:1,自引:0,他引:1
在这篇论文中,我们介绍了一个基于FPGA的网络报文处理硬件平台并且分析了一种基于硬件的防火墙报文检测系统结构。目前的基于软件的防火墙计算量非常大并且不能够满足现代网络带宽的需要。而基于硬件的技术是加速网络处理的一个理想的办法。文章着重介绍了基于FPGA的IP报文过滤处理模块设计,它是基于硬件防火墙的核心处理部分。过滤处理采用关键字匹配策略的重要特征是利用CAM作为处理单元。CAM可以在超过2Gbps的速度下进行线速的入侵检测报文查找。 相似文献
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Ricard Vilalta Raul Muñoz Ramon Casellas Ricardo Martinez Javier Vı´lchez 《Computer Networks》2012,56(13):3123-3135
In this paper we propose a more cost-efficient alternative to current transport network technologies (SONET/SDH) based on the high-bandwidth transport and deterministic performance of the optical circuit technologies (i.e., WSON) along with the efficient aggregation and statistical multiplexing of a packet transport technology (i.e., MPLS-TP) to support IP and Ethernet services. The purpose is to achieve cost reductions, simplified operations and flexible scalability in transport networks. We present the architectural design, implementation and the performance evaluation of the forwarding capabilities of a MPLS-TP/PWE3 node with integrated 10 Gbps tunable DWDM transponders, extending the GMPLS-enabled WSON transport network of the ADRENALINE Testbed. The node has been implemented using commercial off-the-shelf hardware and the forwarding engine has been implemented using open source software. An evaluation of the node is provided by means of analyzing the obtained throughput and CPU usage in different evaluation scenarios with different traffic grooming and traffic aggregation strategies. 相似文献