一种采用单信号控制的新型高压高低侧功率器件

Novel high-voltage, high-side and low-side power devices, whose control circuits are referred to as the tub, are proposed and investigated to reduce chip area and improve the reliability of high-voltage integrated circuits. By using the tub circuit to control a branch circuit consisting of a PMOS and a resistor, a pulse signal is generated to control the low-side n-LDMOS after being processed by a low-voltage circuit. Thus, the high-voltage level-shifting circuit is not needed any more, and the parasitic effect of the conventional level-shifting circuit is eliminated. Moreover, the specific on-resistance of the proposed low-side device is reduced by more than 14.3% compared with the conventional one. In the meantime, integrated low-voltage power supplies for the low-voltage circuit and the tub circuit are also proposed. Simulations are performed with MEDICI and SPICE, and the results show that the expectant functions are achieved well.     

Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.     

一种采用分区RESURF技术并应用多金属环终端技术的新的电平位移结构

A new structure of a lateral n-MOST and a new level-shifting structure with multiply metal rings （MMRs） by divided RESURF technique have been proposed. The device and electrical performances of the structure are analyzed and simulated by MEDICI. In comparison to the level-shifting structure with multiply floating field plates （MFFPs） used before, the structure stated here improves the reliability and diminishes the voltage difference between the voltage of the power supply of the high-side gate driver and the voltage of the output terminal of the level-shifting structure, which is also that of the input terminal of the high-side gate driver. The maximal voltage difference of the level-shifting structure in this paper is 30% lower than that used before. Therefore, good voltage isolation and current isolation are obtained. The structure can be used in the level-shifting circuit of various applications.     

An Ultra Low Steady-State Current Power-on-Reset Circuit in 65nm CMOS Technology

A novel Power-on-reset （POR） circuit is proposed with ultra-low steady-state current consumption. A band=gap voltage eomparator is used to generate a stable pull-up voltage. To eliminate the large current consumptions of the analog part, a power switch is adopted to cut the supply of band-gap voltage comparator, which gained ultra-low current consumption in steady-state after the POR rest process completed. The state of POR circuit is maintained through a state latch circuit. The whole cir- cuit was designed and implemented in 65rim C1V[OS tech- nology with an active area of 120ttm＊160~m. Experimental results show that it has a steady pull=up voltage of 0.69V and a brown-out voltage of 0.49V under a 1.2V supply voltage rising from 0V, plus its steady-state current is only 9hA. The proposed circuit is suitable to be integrated in system on chip to provide a reliable POR signal.     

一种用于高压电平位移电路结构的准三维模拟方法

A new quasi-three-dimensional （quasi-3D） numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.     

一种高可靠性、低功耗单节锂电池保护电路

A single lithium-ion battery protection circuit with high reliability and low power consumption is proposed.The protection circuit has high reliability because the voltage and current of the battery are controlled in a safe range.The protection circuit can immediately activate a protective function when the voltage and current of the battery are beyond the safe range.In order to reduce the circuit’s power consumption,a sleep state control circuit is developed.Additionally,the output frequency of the ring oscillation can be adjusted continuously and precisely by the charging capacitors and the constant-current source.The proposed protection circuit is fabricated in a 0.5 m mixed-signal CMOS process.The measured reference voltage is 1.19 V,the overvoltage is 4.2 V and the undervoltage is 2.2 V.The total power is about 9 W.     

Design of low-voltage and low-power fully integrated filter based on log-domain current-mode integrator

In this paper a novel log-domain current-mode integrator based on MOS transistors in subthreshold is proposed. The integrator's time-constant is tunable by varying a reference bias current. By use of the integrator, a fifth-order Chebyshev lowpass filter with 0.1dB ripples is designed. The simulation results demonstrate that the proposed filter has such advantages as low power supply(1.5V), very low power dissipation (μW level), nearly ideal frequency response, very small sensitivity to components in passband, and adjustable cut-off frequency over a wide range. The circuit is composed of NMOS transistors and grounded capacitors which make it suitable for fully integrated circuit implementation.     

A low-power RF integrated circuit for implantable sensors

A low-power low-voltage analog signal processing circuit has been designed, fabricated, and tested. The circuit is capable of processing an analog sensor current and producing an ASK modulated digital signal with modulating signal frequency proportional to the sensor current level. An on-chip regulator has been included to stabilize the supply voltage received from an external RF power source. The circuit can operate with a power supply as low as 1 V and consumes only about 20 μW of power, which is therefore very suitable for implantable biomedical applications. The whole chip was laid out and fabricated in a 0.35 μm bulk CMOS technology. Experimental results show good agreement with the simulation results.     

FELERION: a new approach for leakage power reduction

The circuit proposed in this paper simultaneously reduces the sub threshold leakage power and saves the state of art aspect of the logic circuits. Sleep transistors and PMOS-only logic are used to further reduce the leakage power. Sleep transistors are used as the keepers to reduce the sub threshold leakage current providing the low resistance path to the output. PMOS-only logic is used between the pull up and pull down devices to mitigate the leakage power further. Our proposed fast efficient leakage reduction circuit not only reduces the leakage current but also reduces the power dissipation. Power and delay are analyzed at the 32 nm BSIM4 model for a chain of four inverters, NAND, NOR and ISCAS-85 c17 benchmark circuits using DSCH3 and the Microwind tool. The simulation results reveal that our proposed approach mitigates leakage power by 90%–94% as compared to the conventional approach.     

A Clock Generator for High-Speed High-Resolution Pipelined A/D Converter Zhao Lei(赵磊) , Yang Yintang(杨银堂), Zhu Zhangming(朱樟明), Liu Lianxi(刘帘羲)

A clock generator circuit for a high-speed high-resolution pipelined A/D converter is presented.The circuit is realized by a delay locked loop(DLL),and a new differential structure is used to improve the precision of the charge pump.Meanwhile,a dynamic logic phase detector and a three transistor NAND logic circuit are proposed to reduce the output jitter by improving the steepness of the clock transition.The proposed circuit,designed by SM1C 0.18μm 3.3 V CMOS technology,is used as a clock generator for a 14 bit 100 MS/s pipelined ADC.The simulation results have shown that the duty cycle ranged from 10%to 90%and can be adjusted.The average duty cycle error is less than 1%.The lock-time is only 13 clock cycles.The active area is 0.05 mm2 and power consumption is less than 15 mW.     

Low-voltage low-power multifunction current-controlled conveyor

In this study, low-voltage low-power multifunction current-controlled conveyor (CCCII) is introduced. Multifunction current conveyors are able to achieve various CCCII structures with a small modification in the circuit. The proposed circuit required ±0.5 V as a power supply, a simple circuit structure and low power consumption. The power consumption is only 4.8 µW. Low-voltage operation is achieved by using changeable threshold voltage and PMOS level-shifter current mirror. This circuit is able to operate as CCCII± with both positive and negative intrinsic resistance, which have a wide tunable range with a small modification in the circuit connections.     

An adaptive high-voltage protection and common-mode adjustment circuit for passive–active continuous-time sigma–delta ADCs

A digitally-programmable circuit is proposed to provide high-voltage protection at start-up, overload, and supply loss conditions in continuous-time passive–active sigma delta ADCs implemented in low-voltage nanometer CMOS technologies. The circuit optimizes the common-mode level at the input stage of the ADC enabling it to interface with input levels beyond its own supply voltage with no impact on device reliability or distortion levels, and minimum impact on area and noise performance, which provides maximum flexibility in the ADC usage. The proposed circuit along with the full ADC is implemented in a typical 65 nm CMOS technology.     

A bulk-driven quasi-floating gate FVF current mirror for low voltage,low power applications

This paper introduces a new low-voltage, low-power FVF current mirror circuit. The bulk-driven (BD) technique is employed to achieve extended input voltage swing and low supply voltage. Besides, the quasi-floating gate (QFG) is used to achieve high frequency performance. The merging of (BD) and (QFG) appear as a good and attractive solution to improve the circuit performance with reduced supply voltage. Benefiting from the interesting properties of (BD-QFG) MOSFET (MOST) technique, the proposed FVF current mirror circuit exhibits superior performance compared to other previously reported works. The workability of the proposed circuit has been verified through ELDO simulator based on a 0.18 μm USMC process. It achieves an enhanced bandwidth (2.7 GHz), low power consumption (79.33 μW), a low input impedance (130 Ω), and high output impedance (9.5 G Ω) from a low supply voltage (0.8 V). Monte Carlo simulation is also carried out, which proves the robust performance of the proposed circuit against mismatches. An application of the proposed current mirror is presented in the form of the current comparator to ensure the workability of the proposed BD-QFG current mirror.     

A low-voltage low-power instrumentation amplifier based on supply current sensing technique

In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.     

基于Cotex-M3内核的智能低压断路器控制器设计

文章介绍了基于Cotex-M3内核的32位高性能微控制器在智能低压断路器控制器的硬件及软件设计中的应用。本智能控制器硬件采用信号变换、波形变换法;软件采用微分法。具体是通过微控制器中集成的PWM输入捕获模式采样变换后的信号来间接计算电流的变化率,大大缩短了过载、短路故障电流的响应时间。智能低压断路器控制器,除实现故障保护功能外,还能对环网供配电系统的现场参数进行实时性监测、区域联网通信等,真正能实现"分布式控制、集中管理",降低现场维护的难度,提高了整个区域环网供配电系统的安全性和可靠性。     

Low voltage folded-mirror mixer

A low-voltage mixer is proposed which uses an RF voltage-to-current converter based on a folded current mirror. Gain, linearity, and frequency performance similar to a traditional high-voltage mixer are achieved with a 1.5-V power supply. Moreover, correct behaviour with a supply voltage as low as 1 V was also simulated     

A single-bit-line cross-point cell activation (SCPA) architecturefor ultra-low-power SRAM's

This paper describes a single-bit-line cross-point cell activation (SCPA) architecture, which has been developed to reduce active power consumption and to avoid increase in the size of high-density SRAM chips, such as 16-Mb SRAM's and beyond. A new PMOS precharging boost circuit, introduced to realize the single-bit-line structure, is also discussed. This circuit is suitable for operation under low-voltage power supply conditions. The SCPA architecture with the new word-line boost circuit is demonstrated with the experimental device, which is fabricated by a 0.4-μm CMOS wafer process technology     

A quasi-3-dimensional simulation method for a high-voltage level-shifting circuit structure

A new quasi-three-dimensional (quasi-3D) numeric simulation method for a high-voltage level-shifting circuit structure is proposed. The performances of the 3D structure are analyzed by combining some 2D device structures; the 2D devices are in two planes perpendicular to each other and to the surface of the semiconductor. In comparison with Davinci, the full 3D device simulation tool, the quasi-3D simulation method can give results for the potential and current distribution of the 3D high-voltage level-shifting circuit structure with appropriate accuracy and the total CPU time for simulation is significantly reduced. The quasi-3D simulation technique can be used in many cases with advantages such as saving computing time, making no demands on the high-end computer terminals, and being easy to operate.